公开(公告)号：US11610858B2

公开(公告)日：2023-03-21

申请号：US17106744

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/683 ,  H01L23/538 ,  H01L25/03 ,  H01L23/31 ,  H01L25/10 ,  H01L21/56 ,  H01L21/48 ,  H01L25/18 ,  H01L25/00

Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming an insulation layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device to the insulation layer and a portion of the plurality of bond pads through hybrid bonding.

公开(公告)号：US11609391B2

公开(公告)日：2023-03-21

申请号：US16877498

申请日：2020-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen

IPC: H01L23/498 ,  H01L21/48 ,  G02B6/42

Abstract: A semiconductor package includes a semiconductor die, a device layer, an insulator layer, a buffer layer, and connective terminals. The device layer is stacked over the semiconductor die. The device layer includes an edge coupler located at an edge of the semiconductor package and a waveguide connected to the edge coupler. The insulator layer is stacked over the device layer and includes a first dielectric material. The buffer layer is stacked over the insulator layer. The buffer layer includes a second dielectric material. The connective terminals are disposed on the buffer layer and reach the insulator layer through contact openings of the buffer layer.

公开(公告)号：US20230067035A1

公开(公告)日：2023-03-02

申请号：US17984379

申请日：2022-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Tzuan-Horng Liu ,  Chao-Wen Shih ,  Sung-Feng Yeh ,  Nien-Fang Wu

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L23/544 ,  H01L23/528 ,  H01L25/00 ,  H01L21/56 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/78 ,  H01L21/683 ,  H01L23/48

Abstract: In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.

公开(公告)号：US11562983B2

公开(公告)日：2023-01-24

申请号：US16737929

申请日：2020-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Sung-Feng Yeh ,  Tzuan-Horng Liu ,  Chao-Wen Shih

IPC: H01L21/78 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L23/48 ,  H01L23/00

Abstract: A package includes an integrated circuit. The integrated circuit includes a first chip, a second chip, a third chip, and a fourth chip. The second chip and the third chip are disposed side by side on the first chip. The second chip and the third chip are hybrid bonded to the first chip. The fourth chip is fusion bonded to at least one of the second chip and the third chip.

公开(公告)号：US11482499B2

公开(公告)日：2022-10-25

申请号：US16989492

申请日：2020-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chia Hu ,  Chun-Chiang Kuo ,  Sen-Bor Jan ,  Ming-Fa Chen ,  Hsien-Wei Chen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/58 ,  H01L23/522 ,  H01L23/532 ,  H01L29/06 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A structure includes a first die and a second die. The first die includes a first bonding layer having a first plurality of bond pads disposed therein and a first seal ring disposed in the first bonding layer. The first bonding layer extends over the first seal ring. The second die includes a second bonding layer having a second plurality of bond pads disposed therein. The first plurality of bond pads is bonded to the second plurality of bond pads. The first bonding layer is bonded to the second bonding layer. An area interposed between the first seal ring and the second bonding layer is free of bond pads.

公开(公告)号：US20220328467A1

公开(公告)日：2022-10-13

申请号：US17383971

申请日：2021-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/498 ,  H01L23/48 ,  H01L23/538 ,  H01L25/00 ,  H01L23/00

Abstract: A package includes an interposer having a first redistribution structure; a first die directly bonded to a first surface of the first redistribution structure with a dielectric-to-dielectric bond and a metal-to-metal bond; a second die directly bonded to the first surface of the first redistribution structure with a dielectric-to-dielectric bond and a metal-to-metal bond; an encapsulant around the first die and the second die; and a plurality of conductive connectors on a second side of the first redistribution structure opposite to the first die and the second die.

公开(公告)号：US11462458B2

公开(公告)日：2022-10-04

申请号：US17181784

申请日：2021-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chia Hu ,  Sen-Bor Jan ,  Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L23/48 ,  H01L23/528 ,  H01L21/768 ,  H01L21/66 ,  H01L23/00

Abstract: A semiconductor device including a test pad contact and a method of manufacturing the semiconductor device are disclosed. In an embodiment, a semiconductor device may include a first metal feature and a second metal feature disposed in a single top metal layer over a substrate. A test pad may be formed over and electrically connected to the first metal feature. A first passivation layer may be formed over the second metal feature and the test pad and may cover top and side surfaces of the test pad. A first via may be formed penetrating the first passivation layer and contacting the test pad and a second via may be formed penetrating the first passivation layer and contacting the second metal feature.

公开(公告)号：US20220310554A1

公开(公告)日：2022-09-29

申请号：US17325667

申请日：2021-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ying-Ju Chen ,  Ming-Fa Chen

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/48 ,  H01L23/544 ,  H01L21/304 ,  H01L21/683 ,  H01L21/768 ,  H01L25/00

Abstract: A method includes placing a first package component. The first package component includes a first alignment mark and a first dummy alignment mark. A second package component is aligned to the first package component. The second package component includes a second alignment mark and a second dummy alignment mark. The aligning is performed using the first alignment mark for positioning the first package component, and using the second alignment mark for position the second package component. The second package component is bonded to the first package component to form a package, with the first alignment mark being bonded to the second dummy alignment mark.

公开(公告)号：US11456240B2

公开(公告)日：2022-09-27

申请号：US17001010

申请日：2020-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Sung-Feng Yeh ,  Ming-Fa Chen ,  Hsien-Wei Chen ,  Tzuan-Horng Liu

IPC: H01L21/56 ,  H01L21/48 ,  H01L21/768 ,  H01L21/683 ,  H01L23/498 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor device and method of manufacture are presented in which a first semiconductor device and second semiconductor device are bonded to a first wafer and then singulated to form a first package and a second package. The first package and second package are then encapsulated with through interposer vias, and a redistribution structure is formed over the encapsulant. A separate package is bonded to the through interposer vias.

公开(公告)号：US20220262766A1

公开(公告)日：2022-08-18

申请号：US17229283

申请日：2021-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chuan-An Cheng ,  Sung-Feng Yeh ,  Chih-Chia Hu

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H01L21/683 ,  H01L21/768 ,  H01L21/56 ,  H01L25/00

Abstract: A method includes bonding a tier-1 device die to a carrier, forming a first gap-filling region to encapsulate the tier-1 device die, forming a first redistribution structure over and electrically connected to the tier-1 device die, and bonding a tier-2 device die to the tier-1 device die. The tier-2 device die is over the tier-1 device die, and the tier-2 device die extends laterally beyond a corresponding edge of the tier-1 device die. The method further includes forming a second gap-filling region to encapsulate the tier-2 device die, removing the carrier, and forming a through-dielectric via penetrating through the first gap-filling region. The through-dielectric via is overlapped by, and is electrically connected to, the tier-2 device die. A second redistribution structure is formed, wherein the first redistribution structure and the second redistribution structure are on opposing sides of the tier-1 device die.