公开(公告)号：US06842135B2

公开(公告)日：2005-01-11

申请号：US10385202

申请日：2003-03-10

Applicant: Arnaud Laflaquiere

Inventor： Arnaud Laflaquiere

IPC: G06J1/00 ,  H03K4/02 ,  H03M1/78

CPC classification number: G06J1/00 ,  H03K4/026

Abstract: A ramp generator includes a resistance ladder (10) supplied with a constant current. Switches are closed in sequence on the resistance ladder to generate the ramp voltage. By using control logic to decode the sequence, a looped shift register is used to close the switches.

Abstract translation: 斜坡发生器包括提供恒定电流的电阻梯（10）。 开关按顺序关闭在电阻梯以产生斜坡电压。 通过使用控制逻辑来解码序列，使用循环移位寄存器来关闭开关。

公开(公告)号：US20040233911A1

公开(公告)日：2004-11-25

申请号：US10794581

申请日：2004-03-05

Applicant: STMICROELECTRONICS LIMITED

Inventor： Matt Morris

IPC: H04L012/28

CPC classification number: H04J3/0632 ,  H04J3/0685

Abstract: A stream processing system is described in which packets of an input stream each include individual timestamps which represent relative delays between the packets. A programmable counter generates continuously count values that are compared with the timestamps in the packet stream. An output controller determines whether or not to release packets from an output port based on the result of the comparison, preferably only releasing packets when the programmable count value equals the timestamp.

Abstract translation: 描述了流处理系统，其中输入流的分组各自包括表示分组之间的相对延迟的各个时间戳。 可编程计数器产生与分组流中的时间戳相比较的连续计数值。 输出控制器基于比较的结果来确定是否从输出端口释放分组，优选地仅当可编程计数值等于时间戳时才释放分组。

公开(公告)号：US20040228342A1

公开(公告)日：2004-11-18

申请号：US10779466

申请日：2004-02-16

Applicant: STMicroelectronics Limited

Inventor： Matt Morris

IPC: H04L012/56

CPC classification number: H04L49/25 ,  H04L49/103

Abstract: The routing of data streams is discussed, and particularly routing one or more incoming streams to one or more output destination ports. The ability to merge incoming streams is discussed so that several low bit rate input packet streams can be merged into a higher bit rate output stream. An assignment data structure identifies for each input stream the or each destination to which it is to be routed, and a packet allocation data structure holds information about the packets and information about the destination of the packets to allow a memory holding the packets to be controlled accordingly.

Abstract translation: 讨论数据流的路由，特别是将一个或多个输入流路由到一个或多个输出目的地端口。 讨论合并输入流的能力，使得几个低比特率输入分组流可以被合并到更高比特率的输出流中。 分配数据结构为每个输入流标识其要路由的每个目的地，并且分组分配数据结构保存关于分组的信息和关于分组的目的地的信息，以允许控制分组的存储器 相应地。

公开(公告)号：US20040119618A1

公开(公告)日：2004-06-24

申请号：US10632564

申请日：2003-08-01

Applicant: STMicroelectronics Limited ,  STMicroelectronics S.r.I.

Inventor： Philip Mattos ,  Marco Losi

IPC: H03M009/00

CPC classification number: H03H17/0664 ,  G01S19/30

Abstract: A semiconductor integrated circuit for processing a plurality of received broadcast signals, such as GPS signals, is operable in two modes: acquisition and tracking. In an acquisition mode, a separate acquisition engine is used which includes a sample reducer for combining samples of a received signal for correlation with a locally generated version of a GPS code. A serial to parallel converter converts the reduced samples to parallel words which are correlated in parallel with locally generated words of the GPS code.

Abstract translation: 用于处理诸如GPS信号的多个接收的广播信号的半导体集成电路可以以两种模式进行操作：采集和跟踪。 在采集模式中，使用单独的采集引擎，其包括用于组合接收信号的采样以与本地生成的GPS码版本进行相关的采样减速器。 串行到并行转换器将缩减的样本转换成与GPS码的本地生成的字并行相关的并行字。

公开(公告)号：US20040119528A1

公开(公告)日：2004-06-24

申请号：US10620834

申请日：2003-07-15

Applicant: STMicroelectronics Limited

Inventor： Tahir Rashid

IPC: G05F003/02

CPC classification number: G05F3/225 ,  G05F3/30

Abstract: The described embodiments of the invention relate to a voltage reference generator which can be produced using new process technologies and which is still compatible with older designs/products. This is achieved by the introduction of circuitry to generate an offset voltage independently of the main reference voltage generation circuitry.

Abstract translation: 所描述的本发明的实施例涉及一种可以使用新的工艺技术制造的并且与旧的设计/产品兼容的电压参考发生器。 这通过引入电路来实现，以产生独立于主参考电压产生电路的偏移电压。

公开(公告)号：US20030185067A1

公开(公告)日：2003-10-02

申请号：US10354908

申请日：2003-01-30

Applicant: STMicroelectronics Limited

Inventor： Andrew Dellow

IPC: G11C007/00

CPC classification number: G06F13/28

Abstract: A semiconductor integrated circuit for use in direct memory access (DMA) has two sources which communicate with a bus through a bus interface. A DMA access signal generator is coupled to the bus interface and asserts a DMA access output signal at a DMA access signal pin whenever either of the sources requires a DMA access. The need for separate DMA access signal pins for each of the two sources is thereby avoided. With targets on two separate integrated circuits, a single DMA access pin can be used for the two targets, while chip select signals at chip select pins on the source integrated circuit indicate which of the two targets is intended for the DMA access.

Abstract translation: 用于直接存储器访问（DMA）的半导体集成电路具有通过总线接口与总线通信的两个源。 DMA访问信号发生器耦合到总线接口，并且每当任何一个源需要DMA访问时，在DMA访问信号引脚处断言DMA访问输出信号。 因此避免了对于两个源中的每一个的单独的DMA访问信号引脚的需要。 通过两个独立的集成电路上的目标，两个目标可以使用单个DMA访问引脚，而源集成电路芯片选择引脚上的芯片选择信号指示两个目标中的哪一个用于DMA访问。

公开(公告)号：US20030177483A1

公开(公告)日：2003-09-18

申请号：US10099455

申请日：2002-03-14

Applicant: STMicroelectronics Limited

Inventor： Trefor Southwell ,  Peter Hedinger

IPC: G06F009/44

CPC classification number: G06F12/126 ,  G06F8/54

Abstract: A method of linking a plurality of object files to generate an executable program, the method comprises identifying in the object files at least one routine to be locked into a cache when the program is executed, locating said routine at a set of memory addresses which man onto a set of cache locations and introducing into the executable program gaps at other sets of memory addresses which map onto the same set of cache locations.

Abstract translation: 一种链接多个对象文件以生成可执行程序的方法，所述方法包括在执行程序时在目标文件中识别要被锁定到高速缓存中的至少一个例程，将所述例程定位在一组存储器地址 到一组缓存位置，并将映射到同一组高速缓存位置的其他存储器地址集合引入可执行程序间隙。

公开(公告)号：US20030137861A1

公开(公告)日：2003-07-24

申请号：US10229337

申请日：2002-08-26

Applicant: STMicroelectronics Limited

Inventor： William Thies ,  Nicolas Froidevaux

IPC: G11C005/06

CPC classification number: H01L27/0207 ,  H01L23/5286 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2224/06153

Abstract: A method of producing a semiconductor circuit is disclosed with an area saving in comparison to conventional circuit layouts. IO cells are arranged with a width multiplied by a factor, but with corresponding reduced height. ESD protection circuitry is included at a reduced rate in comparison to usual arrangements. The space saving is achieved by occupying a semiconductor area that would have been used by ESD circuitry with the IO circuitry. ESD protection is maintained but at different locations.

Abstract translation: 公开了一种制造半导体电路的方法，与常规电路布局相比，具有节省的面积。 IO单元被布置成宽度乘以因子，但具有相应减小的高度。 与常规安排相比，ESD保护电路以降低的速度被包括在内。 通过占用由ESD电路与IO电路一起使用的半导体区域来实现节省空间。 ESD保护保持在不同的位置。

公开(公告)号：US20020154636A1

公开(公告)日：2002-10-24

申请号：US10107602

申请日：2002-03-27

Applicant: STMicroelectronics Limited

Inventor： Tom Thomas

IPC: H04L012/28

CPC classification number: H04L63/0428 ,  H04L45/742

Abstract: A method of locating packet identifiers held in respective memory locations in a memory, the method comprising receiving a plurality of packets, each packet including a packet identifier, searching said memory locations in a sequence to compare an incoming packet identifier with packet identifiers stored in the memory until a match is found, incrementing one of a set of counters associated respectively with the memory locations, said incremented counter being the one associated with the memory location where the match packet identifier is held, and reading values of each of the counters and using said values to determine the sequence in which the memory locations are searched for subsequent incoming packet identifiers.

Abstract translation: 一种定位保存在存储器中的相应存储器位置中的分组标识符的方法，所述方法包括接收多个分组，每个分组包括分组标识符，在序列中搜索所述存储器位置，以将输入分组标识符与存储在 存储器，直到找到匹配，递增与存储器位置相关联的一组计数器中的一个计数器，所述递增计数器是与保持匹配分组标识符的存储器位置相关联的计数器，以及每个计数器的读取值并使用 所述值用于确定搜索存储器位置以用于后续传入分组标识符的顺序。

公开(公告)号：US08572644B2

公开(公告)日：2013-10-29

申请号：US12762132

申请日：2010-04-16

Applicant: Steven Haydock

Inventor： Steven Haydock

IPC: H04N7/10

CPC classification number: H04N21/235 ,  H04N21/434 ,  H04N21/435

Abstract: A data transport device for transporting a data stream, the device including: a data stream processing unit for receiving an input data stream including a plurality of data items, performing processing in dependence on the content of the items and forming an output data stream including at least some of the data items; and a data item injection unit including a memory for storing a plurality of injection data items and associated with each injection data item an injection action, and an injection processor arranged to retrieve the injection action for each of the injection data items in turn and in dependence on the retrieved injection action to inject the associated injection data item into the output data stream.

Abstract translation: 一种用于传送数据流的数据传输装置，该装置包括：数据流处理单元，用于接收包括多个数据项的输入数据流，根据项目的内容执行处理，并形成包括在 最少的一些数据项; 以及数据项目注入单元，其包括用于存储多个注射数据项并且与每个注射数据项相关联的注射动作的存储器，以及喷射处理器，其被配置为依次检索每个注射数据项的注射动作 在检索到的注入动作上将相关联的注入数据项注入到输出数据流中。