公开(公告)号：US20250062230A1

公开(公告)日：2025-02-20

申请号：US18766403

申请日：2024-07-08

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt

IPC: H01L23/528 ,  G11C16/04 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10 ,  H10B43/20

Abstract: A microelectronic device includes a first deck, a second deck, and a first conductive structure. The first deck has one or more memory cell strings and a stack of data lines operably connected to the one or more memory cell strings. Each of the one or more memory cell strings includes a first conductive contact. The second deck is vertically adjacent to the first deck and includes stacked tiers of conductive material defining a first interconnect structure. The first interconnect structure is operably connected to a data line of the stack of data lines. The first conductive structure is electrically coupled to the first conductive contact of the first deck and to the first interconnect structure of the second deck. Methods of forming the microelectronic device are also disclosed, as are memory devices, electronic signal processor devices, and electronic systems comprising such microelectronic devices.

公开(公告)号：US20250061936A1

公开(公告)日：2025-02-20

申请号：US18754884

申请日：2024-06-26

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Haitao Liu

IPC: G11C11/408 ,  G11C11/4091 ,  G11C11/4097 ,  H10B12/00

Abstract: A microelectronic device includes a first die and a second die vertically overlying and attached to the first die. The first die includes an array region and a peripheral region horizontally neighboring the array region. The array region includes memory cells respectively including a first transistor structure, a second transistor structure horizontally neighboring the first transistor structure, and a storage device vertically underlying and coupled to the first transistor structure and the second transistor structure. The peripheral region includes sub word line driver circuitry. The second die includes sense amplifier regions and a CMOS region horizontally neighboring some of the sense amplifier regions. The sense amplifier regions are within a horizontal area of the array region of the first die and include sense amplifier circuitry. The CMOS region horizontally neighbors some of the sense amplifier regions and includes CMOS circuitry. Related memory devices and electronic systems are also described.

公开(公告)号：US20250061070A1

公开(公告)日：2025-02-20

申请号：US18790391

申请日：2024-07-31

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: G06F13/16

Abstract: A memory device (e.g., a high-bandwidth (HBM) memory device) that includes a memory die having multiple pseudo channels per channel is disclosed. The memory die can include first memory banks associated with a first channel (e.g., having a first command address (CA) bus) and a first pseudo channel (e.g., having a first data (DQ) bus) and second memory banks associated with the first channel and a second pseudo channel (e.g., having a second DQ bus). Operations can be performed at the first memory banks or the second memory banks in response to a command received through the first CA bus. The operations can cause data to be returned to circuitry that routes the data to an interface to the first DQ bus or an interface to the second DQ bus based on whether the data resulted from operations at the first memory banks or the second memory banks.

公开(公告)号：US20250061065A1

公开(公告)日：2025-02-20

申请号：US18781989

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Melky Arputharaja Siluvainathan

IPC: G06F13/12 ,  G06F13/24

Abstract: A first set of parameter values are programed to a first set of sequencer registers. A second set of parameter values are programmed to a second set of sequencer registers. In response to a detecting a triggering event, a hardware sequencer performs the following operations: transfer the first set of parameter values from the first set of sequencer registers to a first set of link training registers, transfer the second set of parameter values from the second set of sequencer registers to a second set of link training registers, and initiate one end of a communication link training with a host.

公开(公告)号：US20250061058A1

公开(公告)日：2025-02-20

申请号：US18778600

申请日：2024-07-19

Applicant: Micron Technology, Inc.

Inventor： John M. Gonzales ,  Christopher G. Wieduwilt ,  Seth A. Eichmeyer ,  Matthew D. Jenkinson

IPC: G06F12/02 ,  G06F11/10

Abstract: Apparatuses, systems, and methods for block status parity data are described. An example method includes storing block status data associated with at least one block of a non-volatile memory that indicates a status of the at least one block of memory within a controller. The example method further comprises storing parity data that corresponds to the block status data. The example method further comprises prior to writing the block status data to the non-volatile memory, comparing the stored block status data to the parity data.

公开(公告)号：US20250061056A1

公开(公告)日：2025-02-20

申请号：US18790537

申请日：2024-07-31

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: G06F12/02

Abstract: A memory device (e.g., a high-bandwidth (HBM) memory device) that includes a memory die having multiple pseudo channels per channel is disclosed. The memory die can include first memory banks associated with a first channel (e.g., having a first command address (CA) bus) and a first pseudo channel (e.g., having a first data (DQ) bus) and second memory banks associated with the first channel and a second pseudo channel (e.g., having a second DQ bus). Operations can be performed at the first memory banks or the second memory banks in response to a command received through the first CA bus. The operations can cause data to be returned to circuitry that routes the data to an interface to the first DQ bus or an interface to the second DQ bus based on whether the data resulted from operations at the first memory banks or the second memory banks.

公开(公告)号：US20250061021A1

公开(公告)日：2025-02-20

申请号：US18814142

申请日：2024-08-23

Applicant: Micron Technology, Inc.

Inventor： Crescenzo Attanasio ,  Carminantonio Manganelli ,  Massimo Iaculo ,  Paolo Papa ,  Antonio Eliso

IPC: G06F11/10 ,  G06F3/06 ,  G06F11/07

Abstract: Methods, systems, and devices for device fault condition reporting are described. A host system may transmit, to a memory system, a command to perform an operation. The memory system may receive the command and identify a fault condition associated with performing the operation. The memory system may transmit, to the host system, a message that indicates the fault condition. After the memory system transmits the message, the memory system may enter a safe mode of operation based on identifying the fault condition.

公开(公告)号：US20250061016A1

公开(公告)日：2025-02-20

申请号：US18784572

申请日：2024-07-25

Applicant: Micron Technology, Inc.

Inventor： John M. Gonzales ,  Christopher G. Wieduwilt ,  Seth A. Eichmeyer ,  Matthew D. Jenkinson

IPC: G06F11/10

Abstract: Apparatuses, systems, and methods for block status data reset are described. An example method includes sending a command, from a controller, to access at least one block of a first memory device. The example method further comprises receiving a failure message from the first memory device due to the at least one block being tagged as a bad block in block status data of the first memory device. The example method further comprises in response to receiving the failure message, resetting the block status data by reloading previously stored block status data from a second memory device.

公开(公告)号：US20250060902A1

公开(公告)日：2025-02-20

申请号：US18938813

申请日：2024-11-06

Applicant: Micron Technology, Inc.

Inventor： Reshmi Basu

IPC: G06F3/06 ,  G06F12/02

Abstract: Systems, apparatuses, and methods related to object management in tiered memory systems are discussed. An example method can include determining a type of characteristic set for each of a plurality of memory objects to be written to a memory system. The memory system can include a first memory device and a second memory device. The method can further include configuring each of the plurality of memory objects to be written to the memory system in the first memory device or the second memory device based on the determination of the type of characteristic set associated with each of the plurality of memory objects. The method can further include writing each of the plurality of memory objects to the first memory device or the second memory device based on the configuration of each of the plurality of memory objects.

公开(公告)号：US20250060875A1

公开(公告)日：2025-02-20

申请号：US18933971

申请日：2024-10-31

Applicant: Micron Technology, Inc.

Inventor： Sriteja Yamparala ,  Tawalin Opastrakoon

IPC: G06F3/06

Abstract: A method can include identifying one or more candidate memory blocks that are available for garbage collection, determining a respective erase depth level for each candidate memory block based on one or more block characteristics of the candidate memory block, erasing the candidate memory blocks, wherein each of the candidate memory blocks is erased in accordance with the respective erase depth level determined for the candidate memory block, receiving a request to write data subsequent to erasing the candidate memory blocks, and, responsive to receiving the request to write data, selecting a first memory block from the erased candidate memory blocks in accordance with the respective erase depth level of each of the erased candidate memory blocks. The block characteristics of the candidate memory block can include a program erase count and/or a temperature of the candidate memory block.