公开(公告)号：US09703739B2

公开(公告)日：2017-07-11

申请号：US14590920

申请日：2015-01-06

Applicant: Netronome Systems, Inc.

Inventor： Salma Mirza ,  Gavin J. Stark ,  Steven W. Zagorianakos

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/4027 ,  G06F13/4221

Abstract: In response to receiving a novel “Return Available PPI Credits” command from a credit-aware device, a packet engine sends a “Credit To Be Returned” (CTBR) value it maintains for that device back to the credit-aware device, and zeroes out its stored CTBR value. The credit-aware device adds the credits returned to a “Credits Available” value it maintains. The credit-aware device uses the “Credits Available” value to determine whether it can issue a PPI allocation request. The “Return Available PPI Credits” command does not result in any PPI allocation or de-allocation. In another novel aspect, the credit-aware device is permitted to issue one PPI allocation request to the packet engine when its recorded “Credits Available” value is zero or negative. If the PPI allocation request cannot be granted, then it is buffered in the packet engine, and is resubmitted within the packet engine, until the packet engine makes the PPI allocation.

公开(公告)号：US09641466B2

公开(公告)日：2017-05-02

申请号：US14507643

申请日：2014-10-06

Applicant: Netronome Systems, Inc.

Inventor： Ron Lamar Swartzentruber

IPC: H04L12/861

CPC classification number: H04L49/9084

Abstract: A method for receiving a packet descriptor including a priority indicator and a queue number indicating a queue stored within a first memory unit, storing a packet associated with the packet descriptor in a second memory, determining a first amount of free memory in the first memory unit, determining if the first amount of free memory is above a threshold value, writing the packet from the second memory to a third memory when the first amount of memory is above the threshold value and the priority indicator is equal to a first value, not writing the packet from the second memory unit to the third memory unit if the first amount of memory is below the threshold value or when the priority indicator is equal to a second value. The priority indicator is equal to a first value for high priority packets and a second value for low priority packets.

公开(公告)号：US09641448B1

公开(公告)日：2017-05-02

申请号：US14611231

申请日：2015-01-31

Applicant: Netronome Systems, Inc.

Inventor： Christopher A. Telfer

IPC: H04L12/863 ,  H04L12/721

CPC classification number: H04L47/624 ,  H04L45/38 ,  H04L47/34

Abstract: An Island-Based Network Flow Processor (IB-NFP) receives packets of many flows, and classifies them as belonging to an ordering context. These packets are distributed to a set of Worker Processors (WPs), so that each packet of the context is processed by one WP, but multiple WPs operate on packets of the context at a given time. The WPs use an atomic ticket release functionality of a transactional memory to assist in determining when to release packets to another set of Output Processors (OP). The packets are indicated to the set of OPs in the correct order, even though the WPs may complete their processing of the packets in an out-of-order fashion. For a packet that is indicated as to be released, an OP generates a “transmit command” such that the packet (or a descriptor of the packet) is then put into a properly ordered stream for output from the IB-NFP.

公开(公告)号：US09632959B2

公开(公告)日：2017-04-25

申请号：US14326388

申请日：2014-07-08

Applicant: Netronome Systems, Inc.

Inventor： Rick Bouley

IPC: G06F13/28 ,  G06F13/16

CPC classification number: G06F13/28 ,  G06F13/1663

Abstract: An efficient search key processing method includes writing a first and a second search key data set to a memory, where the search key data sets are written to memory on a word by word basis. Each of the first and second search key data sets includes a header indicating a common lookup operation to be performed and a string of search keys. The header is immediately followed in memory by a search key. The search keys are located contiguously in the memory. At least one word contains search keys from the first and second search key data sets. The memory is read word by word. A first plurality of lookup command messages are sent based on the search keys included in the first search key data set. A second plurality of lookup command messages are sent based on the search keys included in the second search key data set.

公开(公告)号：US09594702B2

公开(公告)日：2017-03-14

申请号：US14326367

申请日：2014-07-08

Applicant: Netronome Systems, Inc.

Inventor： Rick Bouley

IPC: G06F13/16 ,  G06F13/28

CPC classification number: G06F13/1663 ,  G06F13/28

Abstract: A multi-processor includes a shared memory that stores a search key data set including multiple search keys, a processor, a Direct Memory Access (DMA) controller, and an Interlaken Look-Aside (ILA) interface circuit. The processor generates a descriptor that is sent to the DMA controller causing the DMA controller to read the search key data set. The DMA controller selects a single search key from the set and generates a lookup command message that is communicated to the ILA interface circuit. The ILA interface circuit generates an ILA packet that includes the single search key and sends the ILA packet to an external transactional memory device that generates a result data value. The result data value is communicated back to the DMA controller via the ILA interface circuit. The DMA controller stores the result data value in the shared memory and notifies the processor that the DMA process has completed.

Abstract translation: 多处理器包括共享存储器，其存储包括多个搜索键的搜索关键字数据集，处理器，直接存储器访问（DMA）控制器和因特拉肯后视（ILA）接口电路）。 处理器产生一个发送到DMA控制器的描述符，使DMA控制器读取搜索关键字数据集。 DMA控制器从集合中选择单个搜索关键字，并生成传送到ILA接口电路的查找命令消息。 ILA接口电路生成包括单个搜索密钥的ILA分组，并将ILA分组发送到产生结果数据值的外部事务存储器设备。 结果数据值通过ILA接口电路传回DMA控制器。 DMA控制器将结果数据值存储在共享存储器中，并通知处理器DMA进程已完成。

公开(公告)号：US09590926B2

公开(公告)日：2017-03-07

申请号：US14507621

申请日：2014-10-06

Applicant: Netronome Systems, Inc.

Inventor： Ron Lamar Swartzentruber

IPC: H04L12/861

CPC classification number: H04L49/9084

Abstract: An apparatus and method for receiving a packet descriptor and a queue number that indicates a queue stored within a memory unit, determining a first amount of free memory in a group of packet descriptor queues, determining if the first amount of free memory is within a first range, applying a first drop probability to determine if the packet associated with the packet descriptor should be dropped when the first amount of free memory is within the first range, and applying a second drop probability to determine if the packet should be dropped when the first amount of free memory is within a second range. When it is determined that the packet is to be dropped, the packet descriptor is not stored in the queue. When it is determined that the packet is not to be dropped, the packet descriptor is stored in the queue.

Abstract translation: 一种用于接收分组描述符和指示存储在存储器单元中的队列的队列号的装置和方法，确定一组分组描述符队列中的第一空闲存储器量，确定第一量的可用存储器是否在第一 范围，应用第一丢弃概率来确定当所述第一空闲内存量在所述第一范围内时是否应该丢弃与所述分组描述符相关联的分组，以及应用第二丢弃概率来确定当所述第一丢弃概率是否在所述第一 可用内存量在第二范围内。 当确定要丢弃分组时，分组描述符不存储在队列中。 当确定分组不被丢弃时，分组描述符被存储在队列中。

公开(公告)号：US09588928B1

公开(公告)日：2017-03-07

申请号：US14530759

申请日：2014-11-02

Applicant: Netronome Systems, Inc.

Inventor： Ron Lamar Swartzentruber

IPC: G06F13/36 ,  G06F13/40 ,  G06F3/06

CPC classification number: G06F13/4027 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0683

Abstract: A method of performing an unique packet multicast packet ready command (unique packet multicast mode operation) is described herein. A packet ready command is received from a memory system via a bus and onto a network interface circuit. The packet ready command includes a multicast value. A communication mode is determined as a function of the multicast value. The multicast value indicates a plurality of packets are to be communicated to a plurality of destinations by the network interface circuit, and each of the plurality of packets are unique. A free packet command is output from the network interface circuit onto the bus. The free packet command includes a Free On Last Transfer (FOLT) value that indicates that the packets are to be freed from the memory system by the network interface circuit after the packets are communicated to the network interface circuit.

Abstract translation: 本文描述了执行唯一分组多播分组准备命令（唯一分组多播模式操作）的方法。 经由总线和网络接口电路从存储器系统接收到包就绪命令。 分组就绪命令包括多播值。 通信模式被确定为多播值的函数。 组播值表示多个分组将被网络接口电路传送到多个目的地，并且多个分组中的每一个是唯一的。 一个空闲的分组命令从网络接口电路输出到总线上。 空闲分组命令包括自由最后传输（FOLT）值，其指示在分组被传送到网络接口电路之后，网络接口电路将分组从存储器系统中释放出来。

公开(公告)号：US09577832B2

公开(公告)日：2017-02-21

申请号：US14448980

申请日：2014-07-31

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: H04L9/32 ,  G09C1/00

CPC classification number: H04L9/3239 ,  G09C1/00 ,  H04L9/0643 ,  H04L2209/12

Abstract: A processor includes a hash register and a hash generating circuit. The hash generating circuit includes a novel programmable nonlinearizing function circuit as well as a modulo-2 multiplier, a first modulo-2 summer, a modulor-2 divider, and a second modulo-2 summer. The nonlinearizing function circuit receives a hash value from the hash register and performs a programmable nonlinearizing function, thereby generating a modified version of the hash value. In one example, the nonlinearizing function circuit includes a plurality of separately enableable S-box circuits. The multiplier multiplies the input data by a programmable multiplier value, thereby generating a product value. The first summer sums a first portion of the product value with the modified hash value. The divider divides the resulting sum by a fixed divisor value, thereby generating a remainder value. The second summer sums the remainder value and the second portion of the input data, thereby generating a hash result.

Abstract translation: 处理器包括散列寄存器和散列产生电路。 哈希发生电路包括一个新颖的可编程非线性函数电路以及模2乘法器，第一模2夏，模2分频器和第二模2夏。 非线性化函数电路从散列寄存器接收散列值，并执行可编程非线性函数，从而生成散列值的修改版本。 在一个示例中，非线性化功能电路包括多个可单独使能的S盒电路。 乘法器将输入数据乘以可编程乘数值，从而生成乘积值。 第一个夏季用修改的哈希值来计算产品值的第一部分。 分频器将结果总和除以固定除数值，从而生成余数值。 第二个夏天将剩余值和输入数据的第二部分相加，从而生成散列结果。

公开(公告)号：US09489202B2

公开(公告)日：2016-11-08

申请号：US14311212

申请日：2014-06-20

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/82

CPC classification number: G06F9/3802 ,  G06F9/30003 ,  G06F9/30047 ,  G06F9/30069 ,  G06F9/30072 ,  G06F9/30145 ,  G06F9/32 ,  G06F9/3877 ,  G06F9/3881 ,  G06F15/825

Abstract: A pipelined run-to-completion processor has a special tripwire bus port and executes a novel tripwire instruction. Execution of the tripwire instruction causes the processor to output a tripwire value onto the port during a clock cycle when the tripwire instruction is being executed. A first multi-bit value of the tripwire value is data that is output from registers, and/or flags, and/or pointers, and/or data values stored in the pipeline. A field of the tripwire instruction specifies what particular stored values will be output as the first multi-bit value. A second multi-bit value of the tripwire value is a number that identifies the particular processor that output the tripwire value. The processor has a TE enable/disable control bit. This bit is programmable by a special instruction to disable all tripwire instructions. If disabled, a tripwire instruction is fetched and decoded but does not cause the output of a tripwire value.

Abstract translation: 流水线运行到完成处理器具有特殊的tripwire总线端口，并执行新颖的tripwire指令。 在执行tripwire指令时，执行tripwire指令会导致处理器在时钟周期内向端口输出绊线值。 tripwire值的第一多位值是从存储在流水线中的寄存器，/或标志，/或指针和/或数据值输出的数据。 tripwire指令的字段指定将作为第一个多位值输出什么特定的存储值。 tripwire值的第二个多位值是识别输出绊线值的特定处理器的数字。 处理器具有TE使能/禁止控制位。 该位可通过特殊指令进行编程，以禁用所有tripwire指令。 如果禁用，则取出并解码tripwire指令，但不会导致tripwire值的输出。

公开(公告)号：US09483439B2

公开(公告)日：2016-11-01

申请号：US14251599

申请日：2014-04-12

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F15/80 ,  G06F9/50 ,  G06F9/48 ,  G06F9/38 ,  G06F1/32 ,  G06F9/30

CPC classification number: G06F15/80 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/30047 ,  G06F9/30076 ,  G06F9/38 ,  G06F9/3802 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/4843 ,  G06F9/5027 ,  G06F9/5038 ,  G06F15/8007 ,  G06F15/8046 ,  G06F15/8053 ,  Y02D10/171 ,  Y02D10/24

Abstract: A general purpose PicoEngine Multi-Processor (PEMP) includes a hierarchically organized pool of small specialized picoengine processors and associated memories. A stream of data input values is received onto the PEMP. Each input data value is characterized, and from the characterization a task is determined. Picoengines are selected in a sequence. When the next picoengine in the sequence is available, it is then given the input data value along with an associated task assignment. The picoengine then performs the task. An output picoengine selector selects picoengines in the same sequence. If the next picoengine indicates that it has completed its assigned task, then the output value from the selected picoengine is output from the PEMP. By changing the sequence used, more or less of the processing power and memory resources of the pool is brought to bear on the incoming data stream. The PEMP automatically disables unused picoengines and memories.

Abstract translation: 通用PicoEngine多处理器（PEMP）包括一个分层组织的小型专用微型引擎处理器和相关存储器的池。 数据输入值流被接收到PEMP上。 每个输入数据值被表征，并且从表征确定任务。 Picoengines按顺序选择。 当序列中的下一个微型引擎可用时，然后给出输入数据值以及相关的任务分配。 picoengine然后执行任务。 输出微型引擎选择器以相同的顺序选择微型引线。 如果下一个微微引擎指示它已经完成其分配的任务，则从PEMP输出所选择的微微引擎的输出值。 通过改变所使用的顺序，或多或少地将该池的处理能力和存储器资源承担在输入数据流上。 PEMP自动禁用未使用的打印机和内存。