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公开(公告)号：US11258522B2
公开(公告)日：2022-02-22
申请号：US17024835
申请日：2020-09-18
Applicant: Rambus Inc.
Inventor： Craig E. Hampel , Frederick A. Ware , Richard E. Perego
Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.
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公开(公告)号：US11239855B2
公开(公告)日：2022-02-01
申请号：US17166919
申请日：2021-02-03
Applicant: Rambus Inc.
Inventor： Shankar Tangirala
Abstract: A capacitor-based digital-to-analog-converter produces a level-shifted analog outputs by precharging respective sets of output-generating capacitors to different applied potentials and then floating a common output of the sets of capacitors such that charge is redistributed among the capacitors through the common output to yield, across all the capacitors, a uniform precharge voltage that falls between the different applied potentials.
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公开(公告)号：US11238003B2
公开(公告)日：2022-02-01
申请号：US16734839
申请日：2020-01-06
Applicant: Rambus Inc.
Inventor： Yuanlong Wang
IPC: G06F1/00 , G06F13/42 , G06F1/3237 , G06F1/3206 , G06F1/3234
Abstract: The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.
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公开(公告)号：US20220027093A1
公开(公告)日：2022-01-27
申请号：US17428105
申请日：2020-02-05
Applicant: Rambus Inc.
Inventor： Frederick A. Ware
Abstract: An integrated-circuit memory component receives, as part of respective first and second memory read transactions, a first column access command that identifies a first volume of data and a second column read command that identifies a second volume of data, the second volume of data being constituted by not more than half as many data bits as the first volume of data. In response to receiving the first column access command, the integrated-circuit memory component transmits the first volume of data as N parallel bit-serial data signals over N external signaling links. In response to receiving the second column access command, the integrated-circuit memory component transmits the second volume of data as M parallel bit- serial data signals over M of the N external signaling links, where M is less than N.
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公开(公告)号：US20220005542A1
公开(公告)日：2022-01-06
申请号：US17368018
申请日：2021-07-06
Applicant: Rambus Inc.
Inventor： Scott C. Best , John Eric Linstadt , Paul William Roukema
Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.
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Patent Agency Ranking
公开(公告)号：US20220004472A9
公开(公告)日：2022-01-06
申请号：US16670798
申请日：2019-10-31
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Brent S. Haukness , John Eric Linstadt , Scott C. Best
IPC: G06F11/20 , G11C29/52 , G11C11/4093
Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.
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公开(公告)号：US11211139B2
公开(公告)日：2021-12-28
申请号：US16824005
申请日：2020-03-19
Applicant: Rambus Inc.
Inventor： Yohan U. Frans , Wayne F. Ellis , Akash Bansal
IPC: G11C5/04 , G11C29/50 , G06F13/16 , G01R23/02 , G11C7/22 , G11C29/02 , H03L1/02 , G11C8/18 , G06F11/16 , G06F1/12 , G06F1/08 , G01R23/15 , G01R35/00 , G11C7/04
Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.
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公开(公告)号：US20210399929A1
公开(公告)日：2021-12-23
申请号：US17363132
申请日：2021-06-30
Applicant: Rambus Inc.
Inventor： Robert E. Palmer
Abstract: An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.
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公开(公告)号：US11206020B2
公开(公告)日：2021-12-21
申请号：US16880208
申请日：2020-05-21
Applicant: Rambus Inc.
Inventor： Ian Shaeffer
IPC: H03K19/00 , H03K19/0175 , G11C5/06 , G11C5/14 , G11C7/10 , G11C11/4063 , G11C11/413 , G11C16/06
Abstract: Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.
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公开(公告)号：US20210375351A1
公开(公告)日：2021-12-02
申请号：US17323889
申请日：2021-05-18
Applicant: Rambus Inc.
Inventor： Ian Shaeffer , Ely Tsern , Craig Hampel
IPC: G11C11/4093 , H01L25/065 , H01L25/10 , G11C5/02 , G11C5/04 , G11C5/06 , G11C7/10 , G11C7/22 , G06F13/40 , G06F13/16 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4096
Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.
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