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181.发明授权公开(公告)号：US11709185B2
公开(公告)日：2023-07-25
申请号：US17670858
申请日：2022-02-14
Applicant: STMicroelectronics S.r.l.
Inventor： Michele Vaiana , Calogero Marco Ippolito , Angelo Recchia , Antonio Cicero , Pierpaolo Lombardo
CPC classification number: G01R19/0038 , G01R19/0069 , G05F3/08 , H03B5/04 , H03F1/0205 , H03F3/4565
Abstract: An amplification interface includes first and second differential input terminals, first and second differential output terminals providing first and second output voltages defining a differential output signal, and first and second analog integrators coupled between the first and second differential input terminals and the first and second differential output terminals, the first and second analog integrators being resettable by a reset signal. A control circuit generates the reset signal such that the first and second analog integrators are periodically reset during a reset interval and activated during a measurement interval, receives a control signal indicative of offsets in the measurement sensor current and the reference sensor current, and generates a drive signal as a function of the control signal. First and second current generators coupled first and second compensation circuits to the first and second differential input terminals as a function of a drive signal.
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182.发明公开公开(公告)号：US20230215819A1
公开(公告)日：2023-07-06
申请号：US18121145
申请日：2023-03-14
Applicant: STMicroelectronics S.r.l.
Inventor： Paolo CREMA
IPC: B23K26/354 , H01L23/495 , B23K26/0622
CPC classification number: B23K26/354 , H01L23/49582 , H01L23/49503 , B23K26/0622 , B23K2103/08
Abstract: A leadframe has a die pad area and an outer layer of a first metal having a first oxidation potential. The leadframe is placed in contact with a solution containing a second metal having a second oxidation potential, the second oxidation potential being more negative than the first oxidation potential. Radiation energy is then applied to the die pad area of the leadframe contacted with the solution to cause a local increase in temperature of the leadframe. As a result of the temperature increase, a layer of said second metal is selectively provided at the die pad area of the leadframe by a galvanic displacement reaction. An oxidation of the outer layer of the leadframe is then performed to provide an enhancing layer which counters device package delamination.
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183.发明公开公开(公告)号：US20230210435A1
公开(公告)日：2023-07-06
申请号：US18146259
申请日：2022-12-23
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Alessandro GUMIERO , Luigi DELLA TORRE
CPC classification number: A61B5/332 , A61B5/0006 , A61B5/6823
Abstract: The present disclosure is directed to a solid body for a biomedical device, wearable by a patient and configured to acquire one or more physiological parameters of the patient. The solid body includes a first rigid portion, a second rigid portion and a connection portion of flexible type which couples the first and the second rigid portions to each other; and a control circuitry accommodated inside the first and/or the second rigid portions. The connection portion is interposed between the first and the second rigid portions, is integral therewith and is deformable so as to allow a relative movement of the first and the second rigid portions. The first and the second rigid portions are physically couplable to a first and to a second ECG electrode to couple the solid body to the torso of the patient. When the rigid portions are coupled to the ECG electrodes, the control circuitry is electrically coupled to the ECG electrodes and is configured to acquire, through the ECG electrodes, respective electrical signals indicative of said one or more physiological parameters.
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公开(公告)号：US11696507B2
公开(公告)日：2023-07-04
申请号：US16706567
申请日：2019-12-06
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Domenico Giusti , Carlo Luigi Prelini
CPC classification number: H10N30/2042 , B81B3/0018 , B81B3/0072 , B81B2201/032
Abstract: A MEMS device having a body with a first and a second surface, a first portion and a second portion. The MEMS device further has a cavity extending in the body from the second surface; a deformable portion between the first surface and the cavity; and a piezoelectric actuator arranged on the first surface, on the deformable portion. The deformable portion has a first region with a first thickness and a second region with a second thickness greater than the first thickness. The second region is adjacent to the first region and to the first portion of the body.
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公开(公告)号：US11696504B2
公开(公告)日：2023-07-04
申请号：US17321252
申请日：2021-05-14
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Paolo Ferrari , Flavio Francesco Villa , Lucia Zullino , Andrea Nomellini , Luca Seghizzi , Luca Zanotti , Bruno Murari , Martina Scolari
IPC: H10N10/855 , H10N10/01 , H10N10/17
CPC classification number: H10N10/855 , H10N10/01 , H10N10/17
Abstract: A method of fabricating a thermoelectric converter that includes providing a layer of a Silicon-based material having a first surface and a second surface, opposite to and separated from the first surface by a Silicon-based material layer thickness; forming a plurality of first thermoelectrically active elements of a first thermoelectric semiconductor material having a first Seebeck coefficient, and forming a plurality of second thermoelectrically active elements of a second thermoelectric semiconductor material having a second Seebeck coefficient, wherein the first and second thermoelectrically active elements are formed to extend through the Silicon-based material layer thickness, from the first surface to the second surface; forming electrically conductive interconnections in correspondence of the first surface and of the second surface of the layer of Silicon-based material, for electrically interconnecting the plurality of first thermoelectrically active elements and the plurality of second thermoelectrically active elements, and forming an input electrical terminal and an output electrical terminal electrically connected to the electrically conductive interconnections, wherein the first thermoelectric semiconductor material and the second thermoelectric semiconductor material comprise Silicon-based materials selected among porous Silicon or polycrystalline SiGe or polycrystalline Silicon.
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Patent Agency Ranking
公开(公告)号：US11696072B2
公开(公告)日：2023-07-04
申请号：US17517273
申请日：2021-11-02
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Passoni
Abstract: An electro-acoustical transducer such as a Piezoelectric Micromachined Ultrasonic Transducers is coupled with an adjustable load circuit having a set of adjustable load parameters including resistance and inductance parameters. Starting from at least one resonance frequency or at least one ring-down parameter of the electro-acoustical transducer a set of model parameters is calculated for a Butterworth-Van Dyke (BVD) model of the electro-acoustical transducer. The BVD model includes an equivalent circuit network having a constant capacitance coupled to a RLC branch and the adjustable load circuit is coupled with the electro-acoustical transducer at an input port of the equivalent circuit network of the model of the electro-acoustical transducer. The adjustable load parameters are adjusted as a function of the set of model parameters calculated for the BVD model of the electro-acoustic transducer to increase the bandwidth or the sensitivity of the electro-acoustic transducer.
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187.发明授权公开(公告)号：US11691870B2
公开(公告)日：2023-07-04
申请号：US17164546
申请日：2021-02-01
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Alessandro Tocchio , Lorenzo Corso
CPC classification number: B81B7/007 , B81C1/00246 , B81B2201/0235 , B81B2201/0264 , B81B2207/092 , B81B2207/096 , B81C2201/0132 , B81C2203/0118 , B81C2203/0136 , B81C2203/0771 , B81C2203/0792
Abstract: An integrated semiconductor device includes: a MEMS structure; an ASIC electronic circuit; and conductive interconnection structures electrically coupling the MEMS structure to the ASIC electronic circuit. The MEMS structure and the ASIC electronic circuit are integrated starting from a same substrate including semiconductor material; wherein the MEMS structure is formed at a first surface of the substrate, and the ASIC electronic circuit is formed at a second surface of the substrate, vertically opposite to the first surface in a direction transverse to a horizontal plane of extension of the first surface and of the second surface.
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公开(公告)号：US20230208294A1
公开(公告)日：2023-06-29
申请号：US17560977
申请日：2021-12-23
Applicant: STMicroelectronics S.r.l.
Inventor： Aldo VIDONI , Andrea BARBIERI , Franco CONSIGLIERI
CPC classification number: H02M3/158 , G02B26/0833
Abstract: A DC-DC boost converter includes an inductor coupled between an input voltage and an input node, a first path coupled between the input node and a first output node at which a first output voltage is generated, and a second path coupled between the input node and a second output node at which a second output voltage is generated. The DC-DC boost converter operates in a first operating phase where the first path boosts the first output voltage and where the second path is kept from boosting the second output voltage by the second path being coupled to the first path, and operates in a second operating phase where the second path boosts the second output voltage and where the first path is kept from boosting the first output voltage by the second path not being coupled to the first path.
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公开(公告)号：US11686673B2
公开(公告)日：2023-06-27
申请号：US17217662
申请日：2021-03-30
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Maria Eloisa Castagna , Salvatore Cascino , Viviana Cerantonio , Antonello Santangelo
IPC: G01N21/3504
CPC classification number: G01N21/3504
Abstract: The device is formed in a casing including a support, a spacer body, and a mirror element fixed together. A light-emitting element and a light-receiving element are arranged on a bearing surface of the support and face a reflecting surface of the mirror element. The light-emitting element is configured to generate infrared radiation, and the light-receiving element is configured to receive light radiation reflected by the reflecting surface. The spacer body has an emission opening housing the light-emitting element and a reception opening housing the light-receiving element; the reception opening comprises a radiation-limitation portion configured to enable entry of reflected light radiation having an angle, with respect to a normal to the bearing surface, of less than a preset value.
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公开(公告)号：US20230194787A1
公开(公告)日：2023-06-22
申请号：US18167392
申请日：2023-02-10
Inventor： Frédéric BOEUF , Luca Maggi
CPC classification number: G02B6/124 , G02B6/34 , G02B6/43 , G02B6/30 , G02B6/12004 , G02B6/136 , G02B2006/12061
Abstract: A photonic integrated circuit chip includes vertical grating couplers defined in a first layer. Second insulating layers overlie the vertical grating coupler and an interconnection structure with metal levels is embedded in the second insulating layers. A cavity extends in depth through the second insulating layers all the way to an intermediate level between the couplers and the metal level closest to the couplers. The cavity has lateral dimensions such that the cavity is capable of receiving a block for holding an array of optical fibers intended to be optically coupled to the couplers.
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