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    MIM capacitor with adjustable capacitance via electronic fuses
    181.
    发明授权
    MIM capacitor with adjustable capacitance via electronic fuses 有权

    公开(公告)号：US11211290B2

    公开(公告)日：2021-12-28

    申请号：US16820961

    申请日：2020-03-17

    Applicant: QUALCOMM Incorporated

    Inventor： Jonghae Kim ,  Jin-Su Ko ,  Beomsup Kim ,  Periannan Chidambaram

    IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02

    Abstract: Certain aspects of the present disclosure are generally directed to techniques and apparatus for adjusting capacitance in one or more metal-insulator-metal (MIM) capacitors in an effort to reduce capacitance variation between semiconductor devices and improve yield during fabrication. One example method for fabricating a semiconductor device generally includes measuring a capacitance value of a MIM capacitor of the semiconductor device, determining the measured capacitance value of the MIM capacitor is above a target capacitance value for the MIM capacitor, and selectively rupturing a set of connections in the MIM capacitor based on the measured capacitance value. Selectively rupturing the set of connections in the MIM capacitor may reduce the capacitance value of the MIM capacitor to a value approximately that of the target capacitance value.

    Trench capacitor component with reduced equivalent series resistance and equivalent series inductance
    184.
    发明授权
    Trench capacitor component with reduced equivalent series resistance and equivalent series inductance 有权

    公开(公告)号：US11145768B2

    公开(公告)日：2021-10-12

    申请号：US16782865

    申请日：2020-02-05

    Applicant: QUALCOMM Incorporated

    Inventor： Jonghae Kim ,  Periannan Chidambaram

    IPC: H01L29/66 ,  H01L29/94 ,  H01L23/522 ,  H01L27/08 ,  H01L21/768

    Abstract: Certain aspects of the present disclosure generally relate to a capacitive element. One example capacitive element generally includes a substrate, a plurality of trench capacitors, an electrically conductive via, a first electrically conductive contact, and a second electrically conductive contact. The trench capacitors intersect the substrate. The electrically conductive via intersects the substrate and is disposed adjacent to at least one of the trench capacitors. The first electrically conductive contact is disposed above the substrate, and the second electrically conductive contact is disposed below the substrate and electrically coupled to the plurality of trench capacitors through the electrically conductive via.

    Integrated circuit package with a magnetic core
    185.
    发明授权
    Integrated circuit package with a magnetic core 有权

    公开(公告)号：US11101228B1

    公开(公告)日：2021-08-24

    申请号：US16789863

    申请日：2020-02-13

    Applicant: QUALCOMM Incorporated

    Inventor： Jonghae Kim ,  Milind Shah ,  Periannan Chidambaram

    IPC: H01L23/00

    Abstract: Aspects of the present disclosure provide an integrated circuit package having an inductive element with a magnetic core. An example integrated circuit package generally includes a semiconductor die, a redistribution layer, and a magnetic core. The semiconductor die includes a metal layer having first conductive traces and conductive pillars coupled to and extending from the metal layer. The redistribution layer is disposed below the semiconductor die and includes second conductive traces. A portion of the first conductive traces, a portion of the conductive pillars, and a portion of the second conductive traces are arranged to form an inductive element disposed below a portion of the semiconductor die. The magnetic core is disposed in the inductive element.

    Varying thickness inductor
    188.
    发明授权
    Varying thickness inductor 有权

    公开(公告)号：US10354795B2

    公开(公告)日：2019-07-16

    申请号：US15242007

    申请日：2016-08-19

    Applicant: QUALCOMM Incorporated

    Inventor： Daeik Daniel Kim ,  Chengjie Zuo ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Robert Paul Mikulka ,  Xiangdong Zhang ,  Jonghae Kim ,  Je-Hsiung Lan

    IPC: H01F7/06 ,  H01F41/04 ,  H01F27/28 ,  H01F17/00

    Abstract: A method includes forming a first conductive spiral and a second conductive spiral of a spiral inductor coupled to a substrate. The second conductive spiral overlays the first conductive spiral. A first portion of an innermost turn of the spiral inductor has a first thickness in a direction perpendicular to the substrate. The first portion of the innermost turn includes a first portion of the first conductive spiral and does not include the second conductive spiral. A second portion of the innermost turn includes a first portion of the second conductive spiral. A portion of an outermost turn of the spiral inductor has a second thickness in the direction perpendicular to the substrate. The second thickness is greater than the first thickness. The portion of the outermost turn includes a second portion of the first conductive spiral and a second portion of the second conductive spiral.

    Stacked substrate inductor
    190.
    发明授权
    Stacked substrate inductor 有权

    公开(公告)号：US10249580B2

    公开(公告)日：2019-04-02

    申请号：US15190158

    申请日：2016-06-22

    Applicant: QUALCOMM Incorporated

    Inventor： Daeik Daniel Kim ,  Changhan Hobie Yun ,  David Francis Berdy ,  Chengjie Zuo ,  Mario Francisco Velez ,  Jonghae Kim

    IPC: H01L23/64 ,  H01F41/04 ,  H01L23/522 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H01L27/08

    Abstract: In conventional device packages, separate standalone inductors are provided and mounted on an interposer substrate along with a die. Separate inductors reduce integration density, decrease flexibility, increase footprint, and generally increase costs. To address such disadvantages, it is proposed to provide a part of an inductor in a substrate below a die. The proposed stacked substrate inductor may include a first inductor in a first substrate, a second inductor in a second a second substrate stacked on the first substrate, and an inductor interconnect coupling the first and second inductors. The core regions of the first and second inductors may overlap with each other at least partially. The proposed stacked substrate inductor may enhance integration density, increase flexibility, decrease footprint, and/or reduce costs.

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