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公开(公告)号:US10903240B2
公开(公告)日:2021-01-26
申请号:US16402713
申请日:2019-05-03
Applicant: QUALCOMM Incorporated
Inventor: Shiqun Gu , Daniel Daeik Kim , Matthew Michael Nowak , Jonghae Kim , Changhan Hobie Yun , Je-Hsiung Jeffrey Lan , David Francis Berdy
IPC: H01L27/12 , H01L23/498 , H01L21/84 , H01L21/8234 , H01L21/304 , H01L27/088 , H01L23/66 , H01L21/306 , H01L21/762 , H01L21/768 , H01L23/528 , H01L27/092 , H01L29/10 , H01L29/66
Abstract: An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.
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公开(公告)号:US10187031B2
公开(公告)日:2019-01-22
申请号:US15151351
申请日:2016-05-10
Applicant: QUALCOMM Incorporated
Inventor: Yunfei Ma , Chengjie Zuo , David Francis Berdy , Daeik Daniel Kim , Changhan Hobie Yun , Je-Hsiung Jeffrey Lan , Mario Francisco Velez , Niranjan Sunil Mudakatte , Robert Paul Mikulka , Jonghae Kim
Abstract: A tunable matching network is disclosed. In a particular example, the matching network includes at least one first inductor in a signal path of the matching network. The matching network includes at least one second inductor outside of the signal path. The matching network includes one or more switches coupled to the at least one second inductor. The one or more switches are configured to selectively enable mutual coupling of the at least one first inductor and the at least one second inductor.
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公开(公告)号:US10074625B2
公开(公告)日:2018-09-11
申请号:US14859323
申请日:2015-09-20
Applicant: QUALCOMM Incorporated
Inventor: Mario Francisco Velez , David Francis Berdy , Changhan Hobie Yun , Jonghae Kim , Chengjie Zuo , Daeik Daniel Kim , Je-Hsiung Jeffrey Lan , Niranjan Sunil Mudakatte , Robert Paul Mikulka
IPC: H01L23/00 , H01L23/13 , H01L23/498
CPC classification number: H01L24/17 , H01L23/13 , H01L23/49816 , H01L24/03 , H01L24/09 , H01L24/11 , H01L2224/023 , H01L2224/0905
Abstract: An integrated circuit device in a wafer level package (WLP) includes ball grid array (BGA) balls fabricated with cavities filled with adhesives for improved solder joint reliability.
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公开(公告)号:US10069474B2
公开(公告)日:2018-09-04
申请号:US15137662
申请日:2016-04-25
Applicant: QUALCOMM Incorporated
Inventor: Changhan Hobie Yun , Chengjie Zuo , Daeik Daniel Kim , Mario Francisco Velez , Niranjan Sunil Mudakatte , Je-Hsiung Jeffrey Lan , David Francis Berdy , Yunfei Ma , Robert Paul Mikulka , Jonghae Kim
IPC: H03H9/05 , H03H9/10 , H03H9/15 , H03H3/02 , H01F17/02 , H05K1/18 , H03H9/54 , H05K3/46 , H05K1/03 , H05K3/00 , H03H3/08 , H03H9/64 , H01F17/00 , H03H7/01 , H03H7/46
Abstract: A device includes an acoustic resonator embedded within an encapsulating structure that at least partially encapsulates the acoustic resonator. The device includes an inductor electrically connected to the acoustic resonator. At least a portion of the inductor is embedded in the encapsulating structure.
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公开(公告)号:US10026546B2
公开(公告)日:2018-07-17
申请号:US15160776
申请日:2016-05-20
Applicant: QUALCOMM Incorporated
Inventor: Changhan Hobie Yun , Chengjie Zuo , Daeik Daniel Kim , Mario Francisco Velez , Niranjan Sunil Mudakatte , Jonghae Kim , David Francis Berdy
Abstract: An apparatus includes a substrate and a three-dimensional (3D) wirewound inductor integrated within the substrate. The apparatus further includes a capacitor coupled to the 3D wirewound inductor.
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公开(公告)号:US09502586B1
公开(公告)日:2016-11-22
申请号:US14853931
申请日:2015-09-14
Applicant: QUALCOMM Incorporated
Inventor: Daeik Daniel Kim , David Francis Berdy , Je-Hsiung Jeffrey Lan , Changhan Hobie Yun , Jonghae Kim
IPC: H01L29/93 , H01L27/108 , H01L21/70 , H01L27/08 , H01L29/66
CPC classification number: H01L27/0808 , H01L21/7624 , H01L21/76264 , H01L21/78 , H01L27/1203 , H01L29/66174 , H01L29/66181 , H01L29/93
Abstract: A symmetric varactor structure may include a first varactor component. The first varactor component may include a gate operating as a second plate, a gate oxide layer operating as a dielectric layer and a body operating as a first plate of an area modulating capacitor. In addition, doped regions may surround the body of the first varactor component. The first varactor component may be supported on a backside by an isolation layer. The symmetric varactor structure may also include a second varactor component electrically coupled to the backside of the first varactor component through a backside conductive layer.
Abstract translation: 对称变容二极管结构可以包括第一变容二极管组件。 第一变容二极管分量可以包括作为第二板操作的栅极,作为电介质层工作的栅极氧化物层和作为区域调制电容器的第一板工作的主体。 此外,掺杂区域可围绕第一变容二极管部件的主体。 第一变容二极管组件可以由隔离层在背面支撑。 对称变容二极管结构还可以包括通过背侧导电层电耦合到第一变容二极管部件的背侧的第二变容二极管部件。
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公开(公告)号:US12267099B2
公开(公告)日:2025-04-01
申请号:US17655351
申请日:2022-03-17
Applicant: QUALCOMM Incorporated
Inventor: David Francis Berdy , Jin Cho , Yu Steve Zhao , Christian Holenstein , Ryan Scott Castro Spring , Jose Cabanillas , Euichan Moon
Abstract: In certain aspects, a system includes a first filter, a second filter, a dummy load, and a switching circuit coupled to the first filter, the second filter, and the dummy load, and coupled to a first antenna and a second antenna. In a first mode, the switching circuit couples the first filter and the second filter to the first antenna, and, in a second mode, the switching circuit couples the first filter and the third filter to the first antenna and couples the second filter to the second antenna. In certain aspects, the dummy load includes a third filter.
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公开(公告)号:US11024454B2
公开(公告)日:2021-06-01
申请号:US15191203
申请日:2016-06-23
Applicant: QUALCOMM Incorporated
Inventor: Daeik Daniel Kim , Mario Francisco Velez , Changhan Hobie Yun , Niranjan Sunil Mudakatte , Jonghae Kim , Chengjie Zuo , David Francis Berdy
Abstract: Disclosed is an inductor device including a first curved metal plate, a second curved metal plate below and substantially vertically aligned with the first curved metal plate, and a first elongated via vertically aligned between the first curved metal plate and the second curved metal plate, the first elongated via configured to conductively couple the first curved metal plate to the second curved metal plate and having an aspect ratio of a width to a height of the first elongated via of at least approximately 2 to 1.
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公开(公告)号:US09875848B2
公开(公告)日:2018-01-23
申请号:US14976973
申请日:2015-12-21
Applicant: QUALCOMM Incorporated
Inventor: David Francis Berdy , Daeik Daniel Kim , Niranjan Sunil Mudakatte , Je-Hsiung Jeffrey Lan , Chengjie Zuo , Changhan Hobie Yun , Mario Francisco Velez , Jonghae Kim
CPC classification number: H01G4/30 , H01G4/01 , H01G4/33 , H01L23/5223 , H01L27/0805 , H01L28/86 , H01L28/87 , H01L29/94
Abstract: An exemplary MIM capacitor may include a first metal plate, a dielectric layer on the first metal plate, a second metal plate on the dielectric layer, a via layer on the second metal plate, and a third metal plate on the via layer where the second metal plate has a tapered outline with a first side and a second side longer than the first side such that the second side provides a lower resistance path for a current flow.
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公开(公告)号:US09780048B1
公开(公告)日:2017-10-03
申请号:US15227919
申请日:2016-08-03
Applicant: QUALCOMM Incorporated
Inventor: David Francis Berdy , Changhan Hobie Yun , Chengjie Zuo , Niranjan Sunil Mudakatte , Mario Francisco Velez , Shiqun Gu , Jonghae Kim
CPC classification number: H01L23/66 , H01L23/5384 , H01L23/642 , H01L23/645 , H01L24/13 , H01L24/45 , H01L25/18 , H01L25/50 , H01L2224/48195 , H01L2924/14 , H01L2924/19042 , H01L2924/19105 , H05K1/0243 , H05K1/025 , H05K1/141
Abstract: An integrated circuit device includes a first substrate having a ground plane. The integrated circuit device also includes a second substrate. The second substrate has a first layer of passive devices. The passive devices include at least one inductor on a first side of the second substrate. The first layer of passive devices is substantially orthogonal to the ground plane and the second substrate supported by the first substrate. An inductor magnetic field is substantially parallel to the ground plane.
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