公开(公告)号：US20150271494A1

公开(公告)日：2015-09-24

申请号：US14661711

申请日：2015-03-18

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Mihir Narendra Mody ,  Niraj Nandan ,  Mahesh Madhukar Mehendale ,  Subrangshu Das ,  Dipan Kumar Mandal ,  Pavan Venkata Shastry

IPC: H04N19/115 ,  G06F13/28 ,  H04N19/423

CPC classification number: H04N19/115 ,  G06F13/28 ,  H04N19/423

Abstract: A low power video hardware engine is disclosed. The video hardware engine includes a video hardware accelerator unit. A shared memory is coupled to the video hardware accelerator unit, and a scrambler is coupled to the shared memory. A vDMA (video direct memory access) engine is coupled to the scrambler, and an external memory is coupled to the vDMA engine. The scrambler receives an LCU (largest coding unit) from the vDMA engine. The LCU comprises N×N pixels, and the scrambler scrambles N×N pixels in the LCU to generate a plurality of blocks with M×M pixels. N and M are integers and M is less than N.

Abstract translation: 公开了一种低功率视频硬件引擎。 视频硬件引擎包括视频硬件加速器单元。 共享存储器耦合到视频硬件加速器单元，并且加扰器耦合到共享存储器。 vDMA（视频直接存储器访问）引擎耦合到加扰器，并且外部存储器耦合到vDMA引擎。 加扰器从vDMA引擎接收LCU（最大编码单元）。 LCU包括N×N个像素，扰频器对LCU中的N×N个像素进行加扰，以产生具有M×M个像素的多个块。 N和M是整数，M小于N.

公开(公告)号：US20150207974A1

公开(公告)日：2015-07-23

申请号：US14599201

申请日：2015-01-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hetul Sanghavi ,  Rajsekhar Allu

IPC: H04N5/235 ,  H04N5/374 ,  H04N5/3725 ,  H04N5/355 ,  H04N5/357

CPC classification number: H04N5/2355 ,  H04N5/345 ,  H04N5/35581

Abstract: Methods and apparatus to generate wide dynamic range images are disclosed. An example apparatus includes a first processing block having first input, second input to receive input data from an image sensor, and first output; a second processing block having third input, fourth input to receive input data from the image sensor, and second output, at least one of the first and second outputs to output a WDR image based on at least two of the first, second, third and fourth inputs; an architecture recognizer having fifth input and third output, the third output to convey an architecture type of the image sensor; a function selector having fourth output to identify at least one of the first and second processing blocks based on the third output; and a sensor adapter having seventh input coupled to the fourth output and having fifth output coupled to the first and third inputs.

Abstract translation: 公开了产生宽动态范围图像的方法和装置。 示例性装置包括具有第一输入的第一处理块，用于从图像传感器接收输入数据的第二输入和第一输出; 具有第三输入的第二处理块，用于接收来自图像传感器的输入数据的第四输入，以及第二输出，第一和第二输出中的至少一个输出，基于第一，第二，第三和第三输入中的至少两个，输出WDR图像; 第四输入; 具有第五输入和第三输出的架构识别器，用于传送图像传感器的架构类型的第三输出; 功能选择器，具有第四输出，用于基于第三输出来识别第一和第二处理块中的至少一个; 以及传感器适配器，其具有耦合到第四输出的第七输入端，并具有耦合到第一和第三输入端的第五输出端。

公开(公告)号：US20150023609A1

公开(公告)日：2015-01-22

申请号：US14335099

申请日：2014-07-18

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Vipul Paladiya ,  Kapil Ahuja

IPC: H04N19/13 ,  H04N19/44 ,  H04N19/172 ,  H04N19/625

CPC classification number: H04N19/44 ,  H04N19/124 ,  H04N19/34 ,  H04N19/423 ,  H04N19/625 ,  H04N19/70

Abstract: A progressive JPEG (joint photographic experts group) decoder is disclosed. The progressive JPEG decoder includes a processing unit that receives a plurality of progressive scans and generates a plurality of modified progressive scans (MPSs). A baseline JPEG decoder, coupled to the processing unit, includes a Huffman decoder, an inverse quantization unit and an inverse transform unit. The Huffman decoder receives a current MPS and generates a set of transform coefficients corresponding to the current MPS. The processing unit adds a set of transform coefficients corresponding to a previous MPS to the set of transform coefficients corresponding to the current MPS, and the processing unit generates quantization indices. The inverse quantization unit estimates inverse quantization values based on the quantization indices. The inverse transform unit estimates inverse transform decoded values based on the estimated inverse quantization values and generates a set of pixels corresponding to the current MPS.

Abstract translation: 公开了一种渐进的JPEG（联合摄影专家组）解码器。 逐行JPEG解码器包括接收多个渐进扫描并产生多个修改的逐行扫描（MPS）的处理单元。 耦合到处理单元的基线JPEG解码器包括霍夫曼解码器，逆量化单元和逆变换单元。 霍夫曼解码器接收当前的MPS并产生与当前MPS对应的一组变换系数。 处理单元将与先前MPS对应的一组变换系数与对应于当前MPS的变换系数组相加，并且处理单元生成量化索引。 逆量化单元基于量化索引来估计反量化值。 逆变换单元基于估计的反量化值估计逆变换解码值，并生成与当前MPS对应的一组像素。

公开(公告)号：US20130114715A1

公开(公告)日：2013-05-09

申请号：US13671344

申请日：2012-11-07

Applicant: Texas Instruments Incorporated

Inventor： Ranga Ramanujam Srinivasan ,  Chaitanya Satish Ghone ,  Mihir Narendra Mody ,  Minhua Zhou

IPC: H04N7/32

CPC classification number: H04N19/895 ,  H04N19/107 ,  H04N19/172 ,  H04N19/39 ,  H04N19/65

Abstract: A method is provided that includes receiving pictures of a video sequence in a video encoder, and encoding the pictures to generate a compressed video bit stream that is transmitted to a video decoder in real-time, wherein encoding the pictures includes selecting a picture to be encoded as a delayed duplicate intra-predicted picture (DDI), wherein the picture would otherwise be encoded as an inter-predicted picture (P-picture), encoding the picture as an intra-predicted picture (I-picture) to generate the DDI, wherein the I-picture is reconstructed and stored for use as a reference picture for a decoder refresh picture, transmitting the DDI to the video decoder in non-real time, selecting a subsequent picture to be encoded as the decoder refresh picture, and encoding the subsequent picture in the compressed bit stream as the decoder refresh picture, wherein the subsequent P-picture is encoded as a P-picture predicted using the reference picture.

Abstract translation: 提供了一种方法，其包括接收视频编码器中的视频序列的图像，并对图像进行编码以生成被实时发送到视频解码器的压缩视频比特流，其中编码图像包括选择图像为 编码为延迟重复帧内预测图像（DDI），其中图像将被编码为帧间预测图像（P图像），将图像编码为帧内预测图像（I图像）以生成DDI 其中，I图像被重建和存储以用作解码器刷新图像的参考图像，以非实时的方式将DDI发送到视频解码器，选择待编码的后续图像作为解码器刷新图像，以及编码 压缩比特流中的后续图像作为解码器刷新图像，其中后续P图像被编码为使用参考图片预测的P图像。

公开(公告)号：US20250103244A1

公开(公告)日：2025-03-27

申请号：US18371338

申请日：2023-09-21

Applicant: Texas Instruments Incorporated

Inventor： Vignesh Raghavendra ,  Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  Sai Karthik Rajaraman ,  Shailesh Ganapat Ghotgalkar ,  Mohammad Asif Farooqui

IPC: G06F3/06

Abstract: An example apparatus includes a read queue to store a first read request to access a first storage, sequencing circuitry coupled to the read queue, and prioritization circuitry coupled to the sequencing circuitry and coupled to the first storage and a second storage via a shared bus. The example sequencing circuitry is to sequence a portion of a second request to access the second storage to be interleaved with a wait interval of the first read request, the second request queued after the first read request. Additionally, the example prioritization circuitry is to generate a first transaction to access the first storage over the shared bus and a second transaction to access the second storage over the shared bus concurrently with the first transaction, the first transaction based on the first read request, the second transaction based on the second request.

公开(公告)号：US12242379B2

公开(公告)日：2025-03-04

申请号：US18082693

申请日：2022-12-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kedar Chitnis ,  Mihir Narendra Mody ,  Prithvi Shankar Yeyyadi Anantha ,  Sriramakrishnan Govindarajan ,  Mohd Farooqui ,  Shailesh Ghotgalkar

IPC: G06F12/02

Abstract: In an example, a method includes storing code for a first central processing unit (CPU) executing a first application in a first region of a memory, and storing code for a second CPU executing a second application in a second region of the memory. The method includes storing shared code for the first CPU and the second CPU in a third region of the memory. The method includes storing read-write data for the first CPU in a fourth region of the memory and storing read-write data for the second CPU in a fifth region of the memory. The method includes translating a first address from a first unique address space for the first CPU to a shared address space in the third region, and translating a second address from a second unique address space for the second CPU to the shared address space in the third region.

公开(公告)号：US20240411563A1

公开(公告)日：2024-12-12

申请号：US18809646

申请日：2024-08-20

Applicant: Texas Instruments Incorporated

Inventor： Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  Prithvi Shankar Yeyyadi Anantha ,  Shailesh Ghotgalkar ,  Kedar Chitnis

IPC: G06F9/4401 ,  G06F12/14 ,  G06F21/57 ,  G06F21/78 ,  H04L9/32

Abstract: An example device includes a first interface configured to couple to a first memory that is configured to store an image that includes a set of slices; a second interface configured to couple to a second memory; and a direct memory access circuit coupled to the first and second interfaces. The direct memory access circuit receives a transaction that specifies a read of a slice of the set of slices; and based on the transaction, reads the slice from the first memory; performs operations to the slice; and stores the slice in the second memory.

公开(公告)号：US12131504B2

公开(公告)日：2024-10-29

申请号：US17538268

申请日：2021-11-30

Applicant: Texas Instruments Incorporated

Inventor： Gang Hua ,  Mihir Narendra Mody ,  Niraj Nandan ,  Shashank Dabral ,  Rajasekhar Reddy Allu ,  Denis Roland Beaudoin

IPC: G06K9/00 ,  G06T1/20 ,  G06T7/90

CPC classification number: G06T7/90 ,  G06T1/20 ,  G06T2207/10024 ,  G06T2207/20208

Abstract: Techniques for image processing including receiving input image data, wherein the input image data includes data associated with a clear color channel, receiving a color offset value associated with a color channel, wherein color values for the color channel are not provided in the input image data, based on the color offset value, generating intermediate estimated color values for the color channel, wherein generating the intermediate estimated color values includes: clipping color values that have a magnitude greater than the color offset value, and adjusting color values that have a magnitude less than the color offset value based on the color offset value, applying a color correction function to the intermediate estimated color values based on the color offset value to determine color corrected estimated color values, and outputting the color corrected estimated color values.

公开(公告)号：US12126549B2

公开(公告)日：2024-10-22

申请号：US18357710

申请日：2023-07-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan Govindarajan ,  Mihir Narendra Mody

IPC: H04L49/90 ,  H04L49/109 ,  H04L67/568 ,  H04L69/22

CPC classification number: H04L49/9042 ,  H04L49/109 ,  H04L67/568 ,  H04L69/22

Abstract: In an example, a system includes a network port that receives a packet; a first memory; a second memory; and a packet analyzer coupled to the network port. The packet analyzer operates to divide the packet into multiple fragments, analyze each of the multiple fragments to determine whether the corresponding fragment has a first priority level or a second, lower, priority level, determine whether to store each of the multiple fragments in the first memory or the second memory based on the priority level determined for that fragment, store each fragment determined to have the first priority level in the first memory, and store each fragment determined to have the second priority level in the second memory. The network port, packet analyzer and the first memory, which may be a cache memory, may be embodied on a chip, and the second memory may be external to the chip.

公开(公告)号：US20240345870A1

公开(公告)日：2024-10-17

申请号：US18748423

申请日：2024-06-20

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Niraj Nandan ,  Mihir Narendra Mody ,  Kedar Satish Chitnis

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4812 ,  G06F9/5027 ,  G06F2209/5018

Abstract: Systems and method are provided for flexibly configuring task schedulers and respectively associated data processing nodes to execute threads of tasks using a hardware thread scheduler (HTS). The data processing nodes may be hardware accelerators, channels of a direct memory access circuit and external nodes such as a processor executing software instructions. Each hardware accelerator is coupled to a respective hardware task scheduler, each channel is coupled to a respective channel task scheduler, and each external node is coupled to a proxy task scheduler. The task schedulers communicate via pending and decrement signals with a hardware scheduler crossbar. With this arrangement, the HTS couples a first subset of task schedulers in a first data processing order with the associated data processing nodes performing the tasks, and couples a second subset of task schedulers in a second data processing order with the associated data processing nodes performing the tasks.