公开(公告)号：US10515793B2

公开(公告)日：2019-12-24

申请号：US15921624

申请日：2018-03-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L29/06

Abstract: A device includes a fin structure, a dielectric layer, a gate a spacer, and an epitaxy structure. The dielectric layer is over the fin structure. The gate is over the dielectric layer. The spacer is on a sidewall of the gate. The spacer has a thickness along a direction parallel to a longitudinal axis of the fin structure, and a distance along the direction from an outer sidewall of the spacer to an end surface of the fin structure is greater than the thickness of the spacer. The epitaxy structure is in contact with the fin structure.

公开(公告)号：US10510890B2

公开(公告)日：2019-12-17

申请号：US16214156

申请日：2018-12-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66

Abstract: A fin-type field effect transistor comprising a substrate, a plurality of insulators, at least one gate stack and strained material portions is described. The substrate has a plurality of fins thereon and the fin comprises a stop layer embedded therein. The plurality of insulators is disposed on the substrate and between the plurality of fins. The at least one gate stack is disposed over the plurality of fins and on the plurality of insulators. The strained material portions are disposed on two opposite sides of the at least one gate stack.

公开(公告)号：US10510755B2

公开(公告)日：2019-12-17

申请号：US16041996

申请日：2018-07-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/092 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor substrate and at least one gate stack. The gate stack is present on the semiconductor substrate, and the gate stack includes at least one work function conductor and a filling conductor. The work function conductor has a recess therein. The filling conductor includes a plug portion and a cap portion. The plug portion is present in the recess of the work function conductor. The cap portion caps the work function conductor.

公开(公告)号：US10483398B2

公开(公告)日：2019-11-19

申请号：US16042164

申请日：2018-07-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L21/28

Abstract: A semiconductor device is provided. The semiconductor device includes a gate stack over a semiconductor substrate. The semiconductor device also includes a protection element over the gate stack, and a top and a bottom of the protection element have different widths. The semiconductor device further includes a spacer over a side surface of the protection element and a sidewall of the gate stack. In addition, the semiconductor device includes a conductive contact electrically connected to a conductive feature over the semiconductor substrate.

公开(公告)号：US20190148287A1

公开(公告)日：2019-05-16

申请号：US15964276

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/288 ,  H01L21/027

Abstract: A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.

公开(公告)号：US20190148214A1

公开(公告)日：2019-05-16

申请号：US15847307

申请日：2017-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/764 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L21/764 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66545

Abstract: A semiconductor device includes a first gate structure disposed over a substrate. The first gate structure extends in a first direction. A second gate structure is disposed over the substrate. The second gate structure extends in the first direction. A dielectric material is disposed between the first gate structure and the second gate structure. An air gap is disposed within the dielectric material.

公开(公告)号：US20190123202A1

公开(公告)日：2019-04-25

申请号：US16226875

申请日：2018-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L29/06 ,  H01L29/51

CPC classification number: H01L29/7851 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, at least two gate spacers, and a gate stack. The substrate has at least one semiconductor fin. The gate spacers are disposed on the substrate. At least one of the gate spacers has a sidewall facing to another of the gate spacers. The gate stack is disposed between the gate spacers. The gate stack includes a high-κ dielectric layer and a gate electrode. The high-κ dielectric layer is disposed on the substrate and covers at least a portion of the semiconductor fin while leaving the sidewall of said at least one gate spacer uncovered. The gate electrode is disposed on the high-κ dielectric layer.

公开(公告)号：US10157795B2

公开(公告)日：2018-12-18

申请号：US15727626

申请日：2017-10-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Wei-Ting Chen

IPC: H01L27/088 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/12 ,  H01L21/84

Abstract: A semiconductor device includes a substrate, a first gate, a second gate, and an insulating structure. The substrate includes a first fin and a second fin. The first gate is disposed over the first fin. The second gate is disposed over the second fin. A gap is formed between the first gate and the second gate, and the gap gets wider toward the substrate. The insulating structure is disposed in the gap. The insulating structure has a top surface and a bottom surface opposite to each other. The bottom surface faces the substrate. An edge of the top surface facing the first gate is curved inward the top surface.

公开(公告)号：US20180350970A1

公开(公告)日：2018-12-06

申请号：US16043111

申请日：2018-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L29/66 ,  H01L23/535 ,  H01L29/417 ,  H01L21/308

CPC classification number: H01L29/785 ,  H01L21/3085 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/6656 ,  H01L29/66795

Abstract: Contact structures, FinFET devices and methods of forming the same are disclosed. One of the contact structures includes a source/drain region, a mask layer, a connector and a shielding pattern. The source/drain region is between two gate stacks. A mask layer is over the gate stacks and has an opening corresponding to the source/drain region. The connector is electrically connected to the source/drain region, penetrates through the opening of the mask layer and protrudes above and below the mask layer. The shielding pattern is between the mask layer and the connector and in physical contact with the mask layer.

公开(公告)号：US10147821B2

公开(公告)日：2018-12-04

申请号：US15715153

申请日：2017-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.