公开(公告)号：US20070171696A1

公开(公告)日：2007-07-26

申请号：US11643009

申请日：2006-12-19

Applicant: Cyrille Dray ,  Stephane Gamet

Inventor： Cyrille Dray ,  Stephane Gamet

IPC: G11C11/22

CPC classification number: H03K17/102 ,  H03K17/693

Abstract: An embodiment of the invention pertains to an nth order selector switch device comprising: a first arm comprising n transistors series-connected between a first input to which a 0-ranking potential is applied, and an output; and a second arm comprising n transistors series-connected between a second input to which a 0-ranking potential is applied, and the output. The device according to the invention also comprises: a means to produce n−1 potentials ranked 1 to n−1 included between the potential ranked 0 and the potential ranked n; and a driving means for the production, from the n+1 potentials ranked 0 to n, of control signals suited to driving the gates of the transistors of the first arm and the gates of the transistors of the second arm so that the transistors of one of the arms are on and the transistors of the other arm are off depending on the value of the n-ranking potential relative to the value of the 0-ranking potential.

Abstract translation: 本发明的一个实施例涉及第n个订单选择器开关装置，包括：第一臂，包括串联连接在施加0级电位的第一输入和输出之间的n个晶体管; 以及第二臂，包括串联连接在施加0级电位的第二输入和输出之间的n个晶体管。 根据本发明的装置还包括：产生潜在排名0和潜在等级为n之间的包括1至n-1的n-1个电位的装置; 以及用于从适于驱动第一臂的晶体管的栅极和第二臂的晶体管的栅极的控制信号产生从0到n的n + 1个电位的驱动装置，使得一个晶体管 根据相对于0级电位值的n级势的值，另一臂的晶体管截止。

公开(公告)号：US07248233B2

公开(公告)日：2007-07-24

申请号：US10701151

申请日：2003-11-04

Applicant: Jean-Michel Moreau

Inventor： Jean-Michel Moreau

IPC: G09G1/06

CPC classification number: G09G1/005 ,  G09G1/04

Abstract: A control circuit of a power supply delivering a supply current to an inductor connected in series with the horizontal deflection yoke of a cathode ray tube display, the inductor being the primary coil of a transformer operatively connected for delivering a rectified low-pass filtered biasing voltage to the anode of the display, the low-pass filtering having a first time constant corresponding to the duration of a plurality of pictures, the control circuit having feedback circuitry for generating a monitoring voltage substantially proportional to the biasing voltage and for controlling the supply current to keep the monitoring voltage equal to a reference voltage; and feedforward circuitry for measuring the cathode current and for adding to the monitoring voltage a compensation voltage corresponding to the cathode current, low-pass filtered with a second time constant corresponding to the duration of a small number of lines and high-pass filtered with the first time constant.

Abstract translation: 电源的控制电路，其向与阴极射线管显示器的水平偏转线圈串联的电感器提供电源电流，所述电感器是变压器的初级线圈，其可操作地连接用于传送经整流的低通滤波偏置电压 所述低通滤波具有对应于多个图像的持续时间的第一时间常数，所述控制电路具有用于产生与所述偏置电压基本成比例的监测电压并用于控制所述电源电流的反馈电路 保持监控电压等于参考电压; 以及用于测量阴极电流的前馈电路，并且用于将与阴极电流相对应的补偿电压加到监视电压上，以对应于少量线路的持续时间的第二时间常数进行低通滤波，并用 第一次常数。

公开(公告)号：US20070153109A1

公开(公告)日：2007-07-05

申请号：US11603280

申请日：2006-11-21

Applicant: Tarek Lule

Inventor： Tarek Lule

IPC: H04N5/335

CPC classification number: H04N5/35554 ,  H01L27/14609 ,  H04N5/343 ,  H04N5/3559 ,  H04N5/37452

Abstract: The present invention concerns an image sensor having a plurality of pixels each including a photosensor, a first node having a first capacitance connected to the photosensor, a second node having a second capacitance and selectively connected to the photosensor, and reading circuitry operable to read independently a first voltage value stored at the first node and a second voltage value stored at the second node.

Abstract translation: 本发明涉及具有多个像素的图像传感器，每个像素包括光电传感器，具有连接到光电传感器的第一电容的第一节点和具有第二电容并且选择性地连接到光电传感器的第二节点以及可独立读取的读取电路 存储在第一节点处的第一电压值和存储在第二节点处的第二电压值。

公开(公告)号：US20070138502A1

公开(公告)日：2007-06-21

申请号：US11639754

申请日：2006-12-15

Applicant: Christophe Mauriac ,  Samuel Menard

Inventor： Christophe Mauriac ,  Samuel Menard

IPC: H01L29/74

CPC classification number: H01L29/47 ,  H01L29/7412 ,  H01L29/7428

Abstract: A vertical thyristor adapted to an HF control, including a cathode region in a P-type base well, a lightly-doped P-type layer next to the base well, a lightly-doped N-type region in the lightly-doped P-type layer, a Schottky contact on the lightly-doped N-type region connected to a control terminal, and a connection between the lightly-doped N-type region and the P-type base well.

Abstract translation: 适用于HF控制器的垂直晶闸管，包括P型基极阱中的阴极区域，靠近基极阱的轻掺杂P型层，轻掺杂P型层中的轻掺杂N型区， 类型层，连接到控制端子的轻掺杂N型区域上的肖特基接触，以及轻掺杂N型区域和P型基极阱之间的连接。

公开(公告)号：US07227412B2

公开(公告)日：2007-06-05

申请号：US11025848

申请日：2004-12-29

Applicant: Jean-Charles Grasset ,  Frédéric Bossu

Inventor： Jean-Charles Grasset ,  Frédéric Bossu

IPC: H03F3/45

CPC classification number: H03G1/04 ,  H03G7/06

Abstract: Attenuation cell comprising first and second differential pairs of bipolar transistors. A gain control device applies a voltage VA−VB between the bases of both differential pairs and comprises a set of three diodes in which a current IA, a current IB and the sum IA+IB of both preceding currents flow, respectively. The two diodes seeing current IB and IA+IB generate a voltage, respectively VB and VC, and the difference between these two voltages is used to generate a value Iz used in a control loop. A desired value Vct is transformed into information Ix, then into information Iy proportional to absolute temperature T, and an error amplifier uses information Iy−Iz and generates currents IA and IB by minimizing this difference.

Abstract translation: 衰减单元包括第一和第二差分双极晶体管对。 增益控制装置在两个差分对的基极之间施加电压VA-VB，并且包括一组三个二极管，其中电流IA，电流IB和前两个电流的和IA + IB分别流动。 看到电流IB和IA + IB的两个二极管分别产生VB和VC的电压，并且使用这两个电压之间的差来产生在控制回路中使用的值Iz。 期望值Vct被转换成信息Ix，然后转换成与绝对温度T成比例的信息Iy，误差放大器使用信息Iy-Iz，并通过最小化该差来产生电流IA和IB。

公开(公告)号：US07225386B2

公开(公告)日：2007-05-29

申请号：US10264312

申请日：2002-10-03

Applicant: Laurent Murillo

Inventor： Laurent Murillo

IPC: H03M13/00

CPC classification number: H03M13/19 ,  H03M13/616

Abstract: Error detection and correction codes are provided. For a word of m bits that is to be coded, a vector with m components, each component corresponding to a bit of the word, is formed. The vector is multiplied, using a computing circuit, by a parity control matrix. The parity control matrix includes at least one couple of complementary lines.

Abstract translation: 提供错误检测和纠正码。 对于要编码的m位的字，形成具有m个分量的矢量，每个分量对应于该字的位。 使用计算电路将矢量乘以奇偶校验控制矩阵。 奇偶校验控制矩阵包括至少一对互补线。

公开(公告)号：US07225098B2

公开(公告)日：2007-05-29

申请号：US10535064

申请日：2002-11-21

Applicant: Xavier Robert

Inventor： Xavier Robert

IPC: G06F9/44

CPC classification number: G06F11/3656

Abstract: The invention concerns a monitoring device (18) integrated to a microprocessor chip (12) executing a series of instructions comprising: device (26) for producing simultaneously several types of monitoring messages of the microprocessor, a buffer (28) divided into several blocks (A, B, C, D, E) each of which is designed to store only messages of one of the types capable of being produced simultaneously, the size of each block depending on the maximum frequency at which the messages can be stored, and device (26) for, each time one or more messages are simultaneously stored in the blocks (A, B, C, D, E) of the buffer (28), storing in a predetermined block (F) of the buffer a coded value representing said block(s) of the buffer.

Abstract translation: 本发明涉及集成到执行一系列指令的微处理器芯片（12）的监视设备（18），包括：用于同时产生微处理器的几种类型的监视消息的设备（26），被分成几个块的缓冲器（28） A，B，C，D，E），其每一个被设计为仅存储能够同时产生的类型之一的消息，每个块的大小取决于可以存储消息的最大频率，以及设备 （26），每当将一个或多个消息同时存储在缓冲器（28）的块（A，B，C，D，E）中时，在缓冲器的预定块（F）中存储代表 所述块的缓冲区。

公开(公告)号：US07224087B2

公开(公告)日：2007-05-29

申请号：US10744333

申请日：2003-12-23

Applicant: Laurent Gonthier ,  Benoit Peron

Inventor： Laurent Gonthier ,  Benoit Peron

IPC: H01H9/54 ,  H03K17/60

CPC classification number: H03K17/725 ,  H03K17/722 ,  Y10T307/937

Abstract: A circuit for controlling a bidirectional switch referenced to a first reference voltage by a control circuit supplied by a first voltage and referenced to a second reference voltage. The supply voltage of the control circuit is connected by a diode to a coupling circuit comprising a node, this node being connected to the collector of an NPN transistor having its emitter connected to the second reference voltage and having its base receiving the output of the control circuit, to a first terminal of a capacitor having its second terminal connected to the first reference voltage, to the emitter of a PNP transistor having its base connected to the collector of the transistor, and having its collector connected to the control terminal of the bidirectional switch.

Abstract translation: 一种用于通过由第一电压提供并参考第二参考电压的控制电路来控制参考第一参考电压的双向开关的电路。 控制电路的电源电压通过二极管连接到包括节点的耦合电路，该节点连接到其发射极连接到第二参考电压的NPN晶体管的集电极，并且其基极接收控制的输出 电路连接到其第二端子连接到第一参考电压的电容器的第一端子到其基极连接到晶体管的集电极的PNP晶体管的发射极，并且其集电极连接到双向的控制端子 开关。

公开(公告)号：US20070113088A1

公开(公告)日：2007-05-17

申请号：US11432727

申请日：2006-05-11

Applicant: Marcus Volp

Inventor： Marcus Volp

IPC: H04L9/00

CPC classification number: G06F21/575 ,  G06F9/4405 ,  G06F15/177

Abstract: A method of secure booting of an SMP architecture apparatus provides for the formation of a secure domain comprising a first processor and a part of a shared memory, before the booting of the operating system of the first processor. The operating system of a second processor is booted only after the reciprocal authentication with the first processor and, in case of authentication, the extension of the secure domain to the second processor.

Abstract translation: 在第一处理器的操作系统引导之前，SMP架构设备的安全引导的方法提供了包括第一处理器和共享存储器的一部分的安全域的形成。 第二处理器的操作系统仅在与第一处理器的相互认证之后被引导，并且在认证的情况下，将安全域的扩展到第二处理器。

公开(公告)号：US07218553B2

公开(公告)日：2007-05-15

申请号：US11215311

申请日：2005-08-30

Applicant: Jean Devin

Inventor： Jean Devin

IPC: G11C11/34

CPC classification number: G11C16/3454 ,  G11C16/10

Abstract: The present invention relates to a method for programming a memory cell having a determined transconductance curve. The programming of the memory cell comprises a series of programming cycles each comprising a step of verifying the state of the memory cell. According to the present invention, the verify step comprises a first read of the memory cell with a first read voltage greater than a reference threshold voltage, and a second read of the memory cell with a second read voltage lower than or equal to the reference threshold voltage. The memory cell is considered not to be in the programmed state if first- and second-read currents flowing through the memory cell are above determined thresholds, and programming voltage pulses are applied to the memory cell while the latter is not in the programmed state. Application in particular to the programming of Flash memory cells.

Abstract translation: 本发明涉及一种用于对具有确定的跨导曲线的存储单元进行编程的方法。 存储器单元的编程包括一系列编程周期，每个编程周期包括验证存储器单元的状态的步骤。 根据本发明，验证步骤包括具有大于参考阈值电压的第一读取电压的存储器单元的第一次读取，以及具有低于或等于参考阈值的第二读取电压的存储器单元的第二次读取 电压。 如果流过存储单元的第一和第二读取电流高于确定的阈值，则存储单元被认为不处于编程状态，并且编程电压脉冲被施加到存储单元而后者不处于编程状态。 特别适用于闪存单元的编程。