公开(公告)号：US07042746B2

公开(公告)日：2006-05-09

申请号：US10902687

申请日：2004-07-30

申请人： Alan Roth

发明人： Alan Roth

IPC分类号： G11C15/00

CPC分类号： G11C15/04 ,  G11C15/00

摘要： A content Addressable memory (CAM) for performing search operations using variable width search data, said CAM comprising a plurality of arrays of CAM cells, each coupled to a respective sub-search data bus, the sub-search buses being confined to form a main search data bus, to which is applied the search data; selector circuits receiving match line signals from respective CAM arrays, the match line signals being indicative of the results of a search and comparison formed in the associated CAM array, the selector circuit being responsive to a mode selection signal for selecting one or more of said match line output signals to be switched to a priority encoder and multiple match resolver (PE-MMR), wherein in a first mode the match line output signals are switched to said PE-MMR and in a second mode groups of match line output signals from selected arrays are switched to said PE-MMR.

公开(公告)号：US07010713B2

公开(公告)日：2006-03-07

申请号：US10352372

申请日：2003-01-27

申请人： Alan Roth ,  Oswald Becca ,  Pedro Ovalle

发明人： Alan Roth ,  Oswald Becca ,  Pedro Ovalle

IPC分类号： G06F1/12 ,  G06F1/06

CPC分类号： G06F5/08

摘要： A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.

公开(公告)号：US07009419B2

公开(公告)日：2006-03-07

申请号：US10687165

申请日：2003-10-16

申请人： James Goodman

发明人： James Goodman

IPC分类号： H03K19/00 ,  H04L9/00

CPC分类号： G06F21/74 ,  G01R31/31704 ,  G01R31/31719 ,  G01R31/318558 ,  G01R31/318588

摘要： A method and circuit for preventing external access to secure data of an integrated circuit while supporting DFT is disclosed. In accordance with the method the integrated circuit is automatically placed into the test mode at integrated circuit power-up from a power-down state. At power up, secure data is other than present within a secure data-path of the integrated circuit. Access is provided to the secure data path via a second data path coupled with the first secure data-path. Via the access path, data other than secure data is provided to the integrated circuit, the data for performing test functions of the integrated circuit operating in the test mode. Once data other than secure data is provided to first secure data path, the test mode is terminated and access via other than the secure ports is disabled. The test mode is only re-entered by powering down the integrated circuit and re-initialising it.

公开(公告)号：US20050147113A1

公开(公告)日：2005-07-07

申请号：US11069635

申请日：2005-02-28

申请人： David Brown

发明人： David Brown

IPC分类号： H04L12/56

CPC分类号： H04L45/00 ,  H04L45/745

摘要： A number of hash tables are accessed concurrently with a different computed index based on a single search key for each hash table. Each index identifies a location in one of the hash tables capable of storing at least one entry. If all indexed locations are used, the entries stored in the lookup table can be reordered so that the new entry can be inserted in one of the locations identified by the computed indexes.

公开(公告)号：US20040123175A1

公开(公告)日：2004-06-24

申请号：US10352372

申请日：2003-01-27

申请人： MOSAID Technologies, Inc.

发明人： Alan Roth ,  Oswald Becca ,  Pedro Ovalle

IPC分类号： G06F001/12

CPC分类号： G06F5/08

摘要： A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.

摘要翻译： 提出了用于将数据从输入时钟重新同步到输出时钟的同步电路。 第一透明锁存器接收与输入时钟同步的数据。 第二透明锁存器从第一透明锁存器接收数据，并输出取决于延迟的输出时钟的数据，延迟的输出时钟是延迟了插入延迟的输出时钟。 输出锁存器从第二透明锁存器接收数据并将数据与输出时钟同步。

公开(公告)号：US20040080335A1

公开(公告)日：2004-04-29

申请号：US10687165

申请日：2003-10-16

申请人： MOSAID Technologies, Inc.

发明人： James Goodman

IPC分类号： H03K019/00

CPC分类号： G06F21/74 ,  G01R31/31704 ,  G01R31/31719 ,  G01R31/318558 ,  G01R31/318588

摘要： A method and circuit for preventing external access to secure data of an integrated circuit while supporting DFT is disclosed. In accordance with the method the integrated circuit is automatically placed into the test mode at integrated circuit power-up from a power-down state. At power up, secure data is other than present within a secure data-path of the integrated circuit. Access is provided to the secure data path via a second data path coupled with the first secure data-path. Via the access path, data other than secure data is provided to the integrated circuit, the data for performing test functions of the integrated circuit operating in the test mode. Once data other than secure data is provided to first secure data path, the test mode is terminated and access via other than the secure ports is disabled. The test mode is only re-entered by powering down the integrated circuit and re-initialising it.

摘要翻译： 公开了一种用于在支持DFT的同时防止外部访问集成电路的安全数据的方法和电路。 根据该方法，集成电路在从掉电状态的集成电路上电时自动进入测试模式。 在上电时，安全数据不同于存在于集成电路的安全数据路径内。 经由与第一安全数据路径耦合的第二数据路径向安全数据路径提供访问。 通过访问路径，除了安全数据之外的数据被提供给集成电路，用于执行在测试模式下操作的集成电路的测试功能的数据。 一旦将安全数据以外的数据提供给第一安全数据路径，则终止测试模式，并且禁用除安全端口之外的访问。 测试模式只能通过关闭集成电路并重新初始化来重新输入。

公开(公告)号：US20040054655A1

公开(公告)日：2004-03-18

申请号：US10625320

申请日：2003-07-23

申请人： MOSAID Technologies, Inc.

发明人： David A. Brown

IPC分类号： G06F007/00

CPC分类号： H04L12/4625 ,  H04L12/4641 ,  Y10S707/959 ,  Y10S707/99931 ,  Y10S707/99933

摘要： Multiple searches of a filtering database increase the time for filtering a data packet received by a switch. A switch including a translator and a filtering database for performing a single search is presented. The translator provides a translated identifier for an identifier associated with a data packet received by the switch. The translated identifier includes a group identifier corresponding to a virtual LAN group (FID) and a group member number corresponding to an identified virtual LAN (VID). The filter data base stores a static entry and a dynamic entry. The static entry stores a forwarding decision for the data packet associated with the translated identifier. The dynamic entry stores a forwarding decision for the data packet associated with the group identifier included in the translated identifier and the group member number set to don't care. The translated identifier allows a filtering database to provide the forwarding decision stored in the static entry or the dynamic entry for the identifier from a single search operation.

摘要翻译： 过滤数据库的多次搜索增加了过滤交换机接收的数据包的时间。 提出了一种包括翻译器和用于执行单次搜索的过滤数据库的开关。 翻译器提供与由交换机接收的数据分组相关联的标识符的翻译标识符。 被翻译的标识符包括对应于虚拟LAN组（FID）的组标识符和对应于所识别的虚拟LAN（VID）的组成员编号。 过滤器数据库存储静态条目和动态条目。 静态条目存储与转换的标识符相关联的数据分组的转发决定。 动态条目存储与包括在翻译的标识符中的组标识符相关联的数据分组的转发决定以及设置为不关心的组成员编号。 翻译的标识符允许过滤数据库从单个搜索操作提供存储在静态条目中的转发决策或用于标识符的动态条目。

公开(公告)号：US20030179631A1

公开(公告)日：2003-09-25

申请号：US10395656

申请日：2003-03-21

申请人： MOSAID Technologies, Inc.

发明人： John Conrad Koob ,  Raymond Jit-Hung Sung ,  Tyler Lee Brandon ,  Duncan George Elliott

IPC分类号： H03K019/177

CPC分类号： H03K17/693

摘要： A column redundancy architecture for arrayed parallel processor devices is disclosed. In particular, daisy chained communication between processing elements is preserved after defective memory columns and their associated processing elements are disabled, by setting a bypass circuit within the processing element to be disabled. An address remapping circuit ensures that spare memory columns and associated processing elements replacing the defective memory columns and processing elements can be addressed in a linear column order. The column redundancy architecture is flexible as it permits replacement of arbitrary numbers of series adjacent processing elements as well as non adjacent processing elements with a minimal impact on device performance.

摘要翻译： 公开了用于阵列并行处理器设备的列冗余架构。 特别地，通过将​​处理元件内的旁路电路设置为禁用，特别地，在缺陷存储器列及其相关联的处理元件被禁用之后，处理元件之间的菊花链式通信被保留。 地址重映射电路确保可以以线性列顺序来寻址替代有缺陷的存储器列和处理元件的备用存储器列和相关联的处理元件。 列冗余架构是灵活的，因为它允许替换任意数量的相邻处理元件以及不相邻的处理元件，对设备性能的影响最小。

公开(公告)号：US20020067296A1

公开(公告)日：2002-06-06

申请号：US10022932

申请日：2001-12-18

申请人： MOSAID Technologies, Inc.

发明人： David A. Brown

IPC分类号： H03M007/00

CPC分类号： H04L12/4641 ,  H04L45/745 ,  H04L49/201 ,  H04L49/351 ,  H04L49/354

摘要： A method and apparatus is provided for translating an L-bit input signal to a W-bit output signal such as a virtual network identification signal to an internal virtual network signal. The translation is performed using a multi-stage lookup. The input signal is portioned into a plurality of subsets of bits. A first index to a first stage is provided by combining a portion of bits and a first delta subset of bits. A second index to a second stage is provided by combining data stored at the first index in the first stage and the a second delta subset of bits. The corresponding output signal is stored at the last index in the last stage. The use of the multi-stage lookup instead of a single-stage lookup reduces the memory required to perform the translation.

公开(公告)号：US5686848A

公开(公告)日：1997-11-11

申请号：US638810

申请日：1996-04-29

申请人： Ian Mes ,  Graham Allan

发明人： Ian Mes ,  Graham Allan

IPC分类号： H03K17/22 ,  H03L7/00

CPC分类号： H03K17/223

摘要： A power up, power down reset circuit formed of charge storage apparatus for receiving and storing charge from one pole of a voltage supply, a pair of complementary field effect transistors having source-drain circuits connected in series aiding direction between the charge storage apparatus and another pole of the voltage supply, apparatus for connecting the one pole of the voltage supply to a gate of one transistor of the pair of transistors, apparatus for applying a voltage derived from the one pole of the voltage supply but having a value reduced from voltage of the voltage supply, to a gate of another transistor of the pair of transistors, and apparatus for providing a reset pulse from a junction between the source-drain circuits of the pair of transistors.

摘要翻译： 一种由电荷存储装置形成的上电复位电路，用于从电压源的一个极接收和存储电荷;一对互补的场效应晶体管，其具有沿电荷存储装置和另一个的串联辅助方向连接的源极 - 漏极电路; 电压源的极点，用于将电压源的一极连接到该对晶体管的一个晶体管的栅极的装置，用于施加从电压源的一个极导出的电压，但具有从 对该晶体管对的另一个晶体管的栅极施加电压，以及用于从该对晶体管的源极 - 漏极电路之间的结点提供复位脉冲的装置。