公开(公告)号：US08427121B2

公开(公告)日：2013-04-23

申请号：US12671364

申请日：2008-07-25

Applicant: Andrew Notman

Inventor： Andrew Notman

IPC: G05F1/577

CPC classification number: H02M3/1588 ,  H02M2001/009 ,  Y02B70/1466

Abstract: A DC-to-DC converter generates multiple outputs from a single input supply using a single inductor. The inductor current can be changed rapidly by connecting the input voltage in either direction across the inductor using switches A to F. In use, current flows from the input supply through the inductor to an output during a charge phase, then current flows from ground through the inductor to the output in a discharge phase. The level of inductor current at the end of the discharge phase is stored. Before the next charge phase for the same output, the input supply is connected across the inductor in a slew phase to bring the inductor current to the stored level. This reduces crosstalk between outputs having different power requirements. Variable frequency noise in the converter is reduced by giving each output the same total time (slew phase+charge phase+discharge phase).

Abstract translation: DC-DC转换器使用单个电感器从单个输入电源产生多个输出。 通过使用开关A至F在电感器上的任一方向上连接输入电压，可以快速改变电感电流。在使用中，电流在充电阶段期间从输入电源通过电感器流向输出，然后电流从地面流过 电感到放电阶段的输出。 存储放电阶段结束时的电感电流电平。 在相同输出的下一个充电阶段之前，输入电源以电压相位跨过电感连接，以使电感电流达到存储电平。 这减少了具有不同功率要求的输出之间的串扰。 通过给出每个输出相同的总时间（转换阶段+充电阶段+放电阶段），可以减少转换器中的可变频率噪声。

公开(公告)号：US08264273B2

公开(公告)日：2012-09-11

申请号：US12744073

申请日：2008-12-08

Applicant: Douglas James Wallace MacFarlane

Inventor： Douglas James Wallace MacFarlane

IPC: G05F1/10

CPC classification number: H02M3/07

Abstract: A method of generating a voltage supply (Vout+, Vout−) from a single input supply (+VDD), comprising connecting at least one flying capacitor (Cf) to at least one reservoir capacitor (CR1, CR2) and to the input supply in repeated cycles so as to generate a voltage on said reservoir capacitor, the cycles differing between at least two modes so that each mode generates a different voltage on said reservoir capacitor the method including changing from an existing one of said modes to enter a new one of said modes during operation, and operating in at least one transitional mode for a period prior to entering fully said new mode.

Abstract translation: 一种从单个输入电源（+ VDD）产生电压源（Vout +，Vout-）的方法，包括将至少一个快速电容器（Cf）连接到至少一个储存电容器（CR1，CR2）和至少一个储存电容器 重复循环，以便在所述储存电容器上产生电压，所述循环在至少两种模式之间不同，使得每种模式在所述储存电容器上产生不同的电压，所述方法包括从现有的所述模式中的一种转换为输入新的 所述模式在操作期间，并且在进入完全所述新模式之前的一段时间内以至少一个过渡模式操作。

公开(公告)号：US08139792B2

公开(公告)日：2012-03-20

申请号：US11826369

申请日：2007-07-13

Applicant: Anthony James Magrath

Inventor： Anthony James Magrath

IPC: H03F99/00

CPC classification number: H03F3/217 ,  H03F1/305 ,  H03F3/3022 ,  H03F3/45475 ,  H03F3/68 ,  H03F2200/03 ,  H03F2200/351 ,  H03F2200/391 ,  H03F2200/421 ,  H03F2203/30027

Abstract: An amplifier circuit (100) has an input stage (OP1) and an output stage (Q1, Q2) operating with different supply voltages and different quiescent voltages. The output stage has a feedback input connected to receive a feedback signal from the output of the output stage. A biasing circuit (602) applies a bias signal (Ioff) to said input stage at an operating level appropriate to establish a quiescent output voltage different from a ground reference level of the input stage. To start up the amplifier with minimal transients at the output, the following steps are performed in sequence: (a) with the output stage disabled, pre-charging the amplifier output over a period of time to a level (Vmid) corresponding to the ground reference level of the input stage; (b) with the biasing circuit effectively disabled and a zero input signal at said signal input, enabling the input and output stages; (c) activating said biasing circuit progressively so as to ramp said bias signal (Ioff) to said operating level over a further period of time, thereby driving the output progressively to said quiescent output voltage. A separate improvement is in the biasing circuit, which uses the actual output stage supply voltage (PVdd) as a reference to define the operating level of said bias signal (Ioff).

Abstract translation: 放大器电路（100）具有在不同的电源电压和不同静态电压下工作的输入级（OP1）和输出级（Q1，Q2）。 输出级具有连接的反馈输入，以从输出级的输出接收反馈信号。 偏置电路（602）以适于建立与输入级的接地参考电平不同的静态输出电压的工作电平向所述输入级施加偏置信号（Ioff）。 为了在输出端以最小的瞬变启动放大器，按顺序执行以下步骤：（a）在禁止输出级的情况下，将放大器输出在一段时间内预充电到与地对应的电平（Vmid） 输入级的参考电平; （b）偏置电路被有效地禁止，并且在所述信号输入处具有零输入信号，使能输入和输出级; （c）逐渐激活所述偏置电路，以便在一段时间内将所述偏置信号（Ioff）斜升到所述工作电平，从而逐渐将输出驱动到所述静态输出电压。 在偏置电路中单独的改进是使用实际的输出级电源电压（PVdd）作为参考来定义所述偏置信号（Ioff）的工作电平。

公开(公告)号：US08068623B2

公开(公告)日：2011-11-29

申请号：US12436909

申请日：2009-05-07

Applicant: John Paul Lesso

Inventor： John Paul Lesso

IPC: H02B1/00

CPC classification number: G01P15/125 ,  B06B1/0292

Abstract: A capacitive transducer circuit includes a capacitive transducer having first and second electrodes. The first and second electrodes are biased by respective first and second bias voltages. An amplifier is connected to receive a first analog signal on an input terminal, the first analog signal being generated by the capacitive transducer, and to generate a second analog signal on an output terminal. A digital feedback circuit is connected between the output terminal of the amplifier and the input terminal of the amplifier. The digital feedback circuit is configured to provide one of said first or second bias voltages. A switched capacitor filter circuit may be arranged between the voltage source and the transducer and may be arranged to filter the output of the voltage source.

Abstract translation: 电容式换能器电路包括具有第一和第二电极的电容换能器。 第一和第二电极被相应的第一和第二偏置电压偏置。 放大器被连接以在输入端子上接收第一模拟信号，第一模拟信号由电容式换能器产生，并在输出端产生第二模拟信号。 数字反馈电路连接在放大器的输出端和放大器的输入端之间。 数字反馈电路被配置为提供所述第一或第二偏置电压之一。 开关电容器滤波器电路可以布置在电压源和换能器之间，并且可以被布置成对电压源的输出进行滤波。

公开(公告)号：US08045724B2

公开(公告)日：2011-10-25

申请号：US12269632

申请日：2008-11-12

Applicant: Alastair Sibbald

Inventor： Alastair Sibbald

IPC: G10K11/36

CPC classification number: G10K11/178 ,  G10K2210/1081 ,  G10K2210/3013

Abstract: A signal processing circuit is intended for use in a noise reduction system, which produces a target filter characteristic that would achieve optimal noise cancellation, the target filter characteristic including a resonant peak at a first frequency. The signal processing circuit comprises an analogue filter, which has an amplitude response that has a peak or trough at a center frequency, and has a phase response that switches polarity at the center frequency and tends to zero with increase or reduction in frequency away from the center frequency. The center frequency in the amplitude response is substantially equal to the first frequency. The analogue filter may be in the form of a series inductive-capacitive-resistive circuit, where the inductive component is in the form of a gyrator.

Abstract translation: 信号处理电路旨在用于降噪系统，其产生将实现最佳噪声消除的目标滤波器特性，该目标滤波器特性包括在第一频率处的谐振峰值。 信号处理电路包括模拟滤波器，其具有在中心频率处具有峰值或谷值的振幅响应，并具有相位响应，该相位响应在中心频率处切换极性，并且随着频率的增加或减少而趋向于零 中心频率。 振幅响应中的中心频率基本上等于第一频率。 模拟滤波器可以是串联电感电容电阻电路的形式，其中感应组件是旋转器的形式。

公开(公告)号：US07781249B2

公开(公告)日：2010-08-24

申请号：US11723514

申请日：2007-03-20

Applicant: Richard I. Laming ,  Mark Begbie ,  Anthony Traynor

Inventor： Richard I. Laming ,  Mark Begbie ,  Anthony Traynor

IPC: H01L21/00

CPC classification number: B81C1/00158 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81C99/004 ,  B81C2201/0109 ,  H04R7/10 ,  H04R7/18 ,  H04R19/005 ,  H04R2307/207 ,  Y10S977/733

Abstract: A MEMS device comprising a flexible membrane that is free to move in response to pressure differences generated by sound waves. A first electrode mechanically coupled to the flexible membrane, and together form a first capacitive plate. A second electrode mechanically coupled to a generally rigid structural layer or back-plate, which together form a second capacitive plate. A back-volume is provided below the membrane. A first cavity located directly below the membrane. Interposed between the first and second electrodes is a second cavity. A plurality of bleed holes connect the first cavity and the second cavity. Acoustic holes are arranged in the back-plate so as to allow free movement of air molecules, such that the sound waves can enter the second cavity. The first and second cavities in association with the back-volume allow the membrane to move in response to the sound waves entering via the acoustic holes in the back-plate.

Abstract translation: 包括柔性膜的MEMS器件，其可响应于由声波产生的压力差而自由移动。 机械地耦合到柔性膜的第一电极，并且一起形成第一电容板。 机械耦合到大致刚性的结构层或背板的第二电极，它们一起形成第二电容板。 在膜的下方提供背部体积。 位于膜下方的第一腔。 介于第一和第二电极之间的是第二腔。 多个排放孔连接第一腔和第二腔。 声孔布置在背板中，以便允许空气分子的自由运动，使得声波可以进入第二腔。 与背容积相关联的第一和第二空腔允许膜响应于通过背板中的声孔进入的声波而移动。

公开(公告)号：US20100105447A1

公开(公告)日：2010-04-29

申请号：US12523589

申请日：2008-01-23

Applicant: Alastair Sibbald ,  Martin Howle

Inventor： Alastair Sibbald ,  Martin Howle

IPC: G10K11/16 ,  H04M1/00

CPC classification number: H04R3/00 ,  G10K11/178 ,  G10K2210/1081 ,  H04R1/1083

Abstract: The invention provides improved ambient noise reduction for ear-worn devices, such as earphones and headphones and for other devices worn upon or used in close proximity to the ear, such as cellular telephone handsets, and it provides, in particular, improvements to “feed-forward” ambient noise-reduction systems. Most feed-forward noise-reduction systems available hitherto purport to operate only below about 1 kHz and, even then, provide only relatively modest amounts of noise reduction. In accordance with this invention, predetermined filter parameters, such as the gain and cut-off frequency of a selected filter stage used in the noise-reduction processing, are mathematically modelled and the model is adjusted in real-time, in response to user-interpretation of a graphical display of a predicted residual noise amplitude spectrum. This allows the user to inspect the predicted residual noise level amplitude spectrum and to iteratively adjust the filter parameters to minimise residual noise in a chosen environment. Instead of being made manually by a user, the iterative adjustments may be automated and implemented under computer control, using known data-fitting methods and/or neural networks.

Abstract translation: 本发明提供了用于诸如耳机和耳机的耳戴设备以及佩戴在耳朵附近或用于其附近的其他设备（诸如蜂窝电话手机）的改进的环境噪声降低，并且特别地提供了对“馈送” 前向“环境降噪系统。 迄今为止，大多数前馈降噪系统仅在低于约1kHz的情况下运行，并且甚至仅提供相对适量的降噪。 根据本发明，在噪声降低处理中使用的诸如所选滤波器级的增益和截止频率之类的预定滤波器参数被数学地建模，并且响应于用户 - 解释预测的残余噪声幅度谱的图形显示。 这允许用户检查预测的残余噪声电平振幅谱，并且迭代地调整滤波器参数以使所选择的环境中的残余噪声最小化。 使用已知的数据拟合方法和/或神经网络，不是由用户手动进行的，而是可以在计算机控制下自动化并实现迭代调整。

公开(公告)号：US07702943B2

公开(公告)日：2010-04-20

申请号：US12117421

申请日：2008-05-08

Applicant: Holger Haiplik ,  Clive Robert Graham

Inventor： Holger Haiplik ,  Clive Robert Graham

IPC: G06F1/04

CPC classification number: G06F21/725

Abstract: A real time clock comprises a counter which stores a count value, the count value representing a time signal. The counter may be written, for example by a host processor (not shown), such that the time signal can be set to any desired value. The real time clock comprises a check register that stores a check value. The content of the check register (i.e. the check value) is modified each time a write operation is performed on the counter. For example, the content of the check register can be updated by a control signal each time a write operation is performed on the counter. The check value stored in the check register is used for determining whether a write operation performed on the counter is an authorized write operation or an unauthorized write operation. The check value may be incremented each time a write operation is performed, replaced with a new random number each time a write operation is performed, or a combination of both.

Abstract translation: 实时时钟包括存储计数值的计数器，该计数值表示时间信号。 计数器可以例如由主处理器（未示出）写入，使得时间信号可以被设置为任何期望值。 实时时钟包括存储检查值的检查寄存器。 每当对计数器执行写入操作时，校验寄存器的内容（即检查值）被修改。 例如，每当在计数器上执行写入操作时，可以通过控制信号来更新检查寄存器的内容。 存储在检查寄存器中的检查值用于确定在计数器上执行的写入操作是否是授权写入操作还是未经授权的写入操作。 每次执行写入操作时，可以增加检查值，每当执行写入操作时，用新的随机数替换，或者两者的组合。

公开(公告)号：US07649480B2

公开(公告)日：2010-01-19

申请号：US11987772

申请日：2007-12-04

Applicant: Alastair Mark Boomer ,  John Paul Lesso

Inventor： Alastair Mark Boomer ,  John Paul Lesso

IPC: H03M1/10

CPC classification number: H03M1/1023 ,  H03M1/1009 ,  H03M1/12

Abstract: A calibration circuit and method suitable for black level calibration in image processing, the circuit comprising an analogue gain amplifier, an analogue to digital converter; a correction circuit for receiving a digital signal and providing a digital offset signal; and a digital to analogue converter for receiving said digital offset signal and feeding a corresponding analogue offset signal back to the input of said gain amplifier. The calibration circuit is arranged such that the correction circuit and said digital to analogue converter form a feedback loop applying an offset to said input signal and said correction circuit includes an inverse gain circuit for applying an inverse gain to a signal within said correction circuit prior to said digital to analogue converter. Preferably the inverse gain applied is such that the total loop gain does not deviate too far from unity.

Abstract translation: 一种适用于图像处理中的黑电平校准的校准电路和方法，该电路包括模拟增益放大器，模数转换器; 用于接收数字信号并提供数字偏移信号的校正电路; 以及数模转换器，用于接收所述数字偏移信号，并将相应的模拟偏移信号反馈给所述增益放大器的输入端。 校准电路被布置成使得校正电路和所述数模转换器形成对所述输入信号施加偏移的反馈环路，并且所述校正电路包括用于在所述校正电路之前对所述校正电路中的信号施加反增益的反相增益电路 表示数模转换器。 优选地，应用的反增益使得总环路增益不会偏离太远离单位。

公开(公告)号：US07579894B2

公开(公告)日：2009-08-25

申请号：US11783579

申请日：2007-04-10

Applicant: Abhay Kejriwal

Inventor： Abhay Kejriwal

IPC: H03K17/16

CPC classification number: H03K5/1252

Abstract: A circuit for debouncing a signal from a switch or other input. The invention provides an arrangement which receives an input signal and which monitors the input to provide an output which switches after a predetermined time from the input signal changing from one state to another. However, the output changes back to its original state in a much shorter time if said input changes back to its original state.

Abstract translation: 用于去除来自开关或其他输入的信号的电路。 本发明提供了一种接收输入信号并且监视输入以提供从输入信号从一个状态改变到另一个状态的预定时间之后切换的输出的装置。 然而，如果所述输入改变回到其原始状态，则输出在更短的时间内变回其初始状态。