Printed circuit board assembly for automatic test equipment
    11.
    发明授权
    Printed circuit board assembly for automatic test equipment 失效
    用于自动测试设备的印刷电路板组件

    公开(公告)号:US06882156B2

    公开(公告)日:2005-04-19

    申请号:US10076757

    申请日:2002-02-14

    申请人: Steven Hauptman

    发明人: Steven Hauptman

    摘要: A printed circuit board assembly adapted for immersion cooling is disclosed. The assembly includes a first circuit board having a first device side with a first portion configured to mount a first plurality of semiconductor devices. A second circuit board having a second device side with a second portion configured to mount a second plurality of semiconductor devices is disposed in confronting parallel relationship to the first circuit board. The assembly further includes a border element interposed between the first and second boards and disposed around the respective first and second portions. The border element cooperates with the first and second boards to form a liquid-tight container. An inlet formed in the border receives an electrically nonconducting liquid that is subsequently discharged through an outlet.

    摘要翻译: 公开了一种适用于浸没冷却的印刷电路板组件。 该组件包括具有第一器件侧的第一电路板,第一器件侧具有构造成安装第一多个半导体器件的第一部分。 具有第二装置侧的第二电路板与配置成安装第二多个半导体装置的第二部分以与第一电路板相对的平行关系设置。 组件还包括插入在第一和第二板之间并且围绕相应的第一和第二部分设置的边界元件。 边界元件与第一和第二板协作以形成液密容器。 在边界处形成的入口接收电气不导液,随后通过出口排出。

    High speed connector assembly
    12.
    发明授权
    High speed connector assembly 有权
    高速连接器总成

    公开(公告)号:US07048585B2

    公开(公告)日:2006-05-23

    申请号:US10744328

    申请日:2003-12-23

    IPC分类号: H01R13/648

    摘要: There is disclosed a two-piece electrical connector assembly having a first electrical connector and a second electrical connector. The first electrical connector includes a plurality of first signal conductors disposed along first and second sides of a first insulative housing and first ground plates disposed along the first and second sides of the first insulative housing and positioned adjacent the plurality of first signal conductors. The first electrical connector defines a slot for receiving an edge of a first printed circuit board. The second electrical connector includes a plurality of second signal conductors disposed along first and second sides of a second insulative housing and second ground plates disposed along the first and second sides of the second insulative housing and positioned adjacent the plurality of second signal conductors. Each of the second ground plates has a surface with a first edge and a second edge, at least one of the first edge or the second edge being bent in the direction toward the corresponding second signal conductor. When the first electrical connector and the second electrical connector are mated, the first signal conductors and corresponding second signal conductors are substantially enclosed and shielded by the first and second ground plates.

    摘要翻译: 公开了一种具有第一电连接器和第二电连接器的两件式电连接器组件。 第一电连接器包括沿着第一绝缘壳体的第一和第二侧布置的多个第一信号导体和沿着第一绝缘壳体的第一和第二侧布置并且邻近多个第一信号导体定位的第一接地板。 第一电连接器限定用于接收第一印刷电路板的边缘的槽。 第二电连接器包括沿着第二绝缘壳体的第一和第二侧布置的多个第二信号导体和沿着第二绝缘壳体的第一和第二侧布置并且邻近多个第二信号导体定位的第二接地板。 每个第二接地板具有具有第一边缘和第二边缘的表面,第一边缘或第二边缘中的至少一个沿着朝向相应的第二信号导体的方向弯曲。 当第一电连接器和第二电连接器配合时,第一信号导体和对应的第二信号导体基本上被第一和第二接地板封闭和屏蔽。

    Hybrid tester architecture
    13.
    发明授权
    Hybrid tester architecture 失效
    混合测试仪架构

    公开(公告)号:US06885961B2

    公开(公告)日:2005-04-26

    申请号:US10090585

    申请日:2002-02-28

    CPC分类号: G01R31/31922 G01R31/31928

    摘要: A hybrid tester architecture for testing a plurality of semiconductor devices in parallel is disclosed. The hybrid tester architecture includes per-pin formatting circuitry having data input circuitry and clock input circuitry and shared timing circuitry coupled to the clock input circuitry. The shared timing circuitry generates programmed timing signals. Per-pin data circuitry couples to the data input circuitry and generates drive data and expected data values associated with each individual device pin. The per-pin formatting circuitry responds to the programmed timing signals to produce tester waveforms in accordance with the per-pin data.

    摘要翻译: 公开了一种并行测试多个半导体器件的混合测试器架构。 混合测试器架构包括具有数据输入电路和时钟输入电路的每引脚格式化电路以及耦合到时钟输入电路的共享定时电路。 共享定时电路产生编程定时信号。 每针数据电路耦合到数据输入电路,并产生与各个器件引脚相关联的驱动数据和预期数据值。 每针式格式化电路响应编程的定时信号,以根据每针数据产生测试仪波形。

    Discrete fourier transform (DFT) leakage removal
    14.
    发明授权
    Discrete fourier transform (DFT) leakage removal 失效
    离散傅立叶变换(DFT)泄漏去除

    公开(公告)号:US06882947B2

    公开(公告)日:2005-04-19

    申请号:US10036000

    申请日:2001-12-31

    申请人: Harold J. Levin

    发明人: Harold J. Levin

    IPC分类号: G01R23/16 G06F19/00

    CPC分类号: G01R23/16

    摘要: A technique for measuring spectral components, such as noise and distortion, of a non-coherently sampled test signal containing at least one tone of known frequency includes modeling the spectral components of the at least one tone, including the effects of leakage, based upon frequency of the at least one tone and a plurality of known sampling parameters. A DFT is taken of the sampled test signal, and the DFT is adjusted based on the modeled spectral components. The adjusted DFT is substantially leakage-free and directly reveals spectral components of the test signal, including low-power components that would ordinarily be lost in the leakage errors.

    摘要翻译: 用于测量包含已知频率的至少一个音调的非相干采样的测试信号的频谱分量(诸如噪声和失真)的技术包括基于频率对包括泄漏的影响在内的至少一个音调的频谱分量进行建模 的至少一个音调和多个已知的采样参数。 对采样的测试信号进行DFT,并根据建模的频谱分量调整DFT。 经调整的DFT基本上是无泄漏的,并直接显示测试信号的频谱分量,包括通常在泄漏误差中丢失的低功率分量。

    Hybrid AC/DC-coupled channel for automatic test equipment
    15.
    发明授权
    Hybrid AC/DC-coupled channel for automatic test equipment 有权
    用于自动测试设备的混合AC / DC耦合通道

    公开(公告)号:US06879175B2

    公开(公告)日:2005-04-12

    申请号:US10404900

    申请日:2003-03-31

    申请人: George W. Conner

    发明人: George W. Conner

    IPC分类号: G01R31/28 G01R31/26

    CPC分类号: G01R31/2844

    摘要: A channel for use in automatic test equipment and adapted for coupling to a device-under-test is disclosed. The channel includes a driver and respective AC and DC-coupled signal paths. The AC-coupled signal path is disposed at the output of the driver and is configured to propagate signal components at and above a predetermined frequency. The DC-coupled signal path is disposed in parallel with the AC-coupled signal path and is configured to propagate signal components from DC to the predetermined frequency.

    摘要翻译: 公开了一种用于自动测试设备并适用于耦合到被测设备的通道。 该通道包括驱动器和相应的AC和DC耦合信号路径。 交流耦合信号路径设置在驱动器的输出处,并且被配置为在预定频率上和之上传播信号分量。 DC耦合信号路径与AC耦合信号路径平行设置,并且被配置为将信号分量从DC传播到预定频率。

    Compact ATE with time stamp system
    16.
    发明授权
    Compact ATE with time stamp system 有权
    紧凑型ATE带时间戳系统

    公开(公告)号:US06868047B2

    公开(公告)日:2005-03-15

    申请号:US10015865

    申请日:2001-12-12

    摘要: A accurate time measurement circuit. The design is amenable to implementation as a CMOS integrated circuits, making the circuit suitable for a highly integrated system, such as automatic test equipment where multiple time measurement circuits are required. The circuit uses a delay locked loop to generate a plurality of signals that are delayed in time by an interval D. The signal to be measured is fed to a bank of delay elements, each with a slightly different delay with the difference in delay between the first and the last being more than D. An accurate time measurement is achieved by finding coincidence between one of the TAP signals and one of the delay signals. The circuit has much greater accuracy than a traditional delay line based time measurement circuit with the same number of taps. It therefore provides both accuracy and fast re-fire time and is less susceptible to noise.

    摘要翻译: 精确的时间测量电路。 该设计适合作为CMOS集成电路的实现,使得该电路适合于高度集成的系统,例如需要多个时间测量电路的自动测试设备。 电路使用延迟锁定环来产生在时间上延迟了一段时间的多个信号。待测量的信号被馈送到一组延迟元件,每个延迟元件具有稍微不同的延迟,延迟元件之间的延迟差异 首先和最后一个超过D.通过发现一个TAP信号和一个延迟信号之间的一致性来实现准确的时间测量。 该电路具有比具有相同数量的抽头的传统的基于延迟线的时间测量电路具有更大的精度。 因此,它提供准确性和快速重燃时间,并且不易受噪音影响。

    Automatic test manipulator with support internal to test head
    17.
    发明授权
    Automatic test manipulator with support internal to test head 有权
    自动测试机械手,内部支持测试头

    公开(公告)号:US06837125B1

    公开(公告)日:2005-01-04

    申请号:US09615292

    申请日:2000-07-13

    IPC分类号: G01R31/28 G05G11/00

    摘要: A manipulator for accurately positioning a test head in automatic test systems supports the test head internally and reduces the overall size of the manipulator. The manipulator includes an elongated blade that extends into a central region of the test head. A spherical bearing is disposed within an opening of the elongated blade, and has an outlet race attached to the elongated blade. A shaft passes through the inner race of the spherical bearing and attaches to the body of the test head via a transition insert. The test head can thus be supported internally and made to rotate in compliance on the spherical bearing, about all axes of rotation.

    摘要翻译: 用于将测试头精确定位在自动测试系统中的操纵器在内部支撑测试头,并减小操纵器的总体尺寸。 操纵器包括延伸到测试头的中心区域的细长叶片。 球形轴承设置在细长刀片的开口内,并且具有附接到细长刀片的出口座圈。 轴通过球面轴承的内圈并通过过渡插入件连接到测试头的主体。 因此,测试头可以内部支撑并使其在球面轴承上绕所有旋转轴线顺时针旋转。