公开(公告)号：US20250079328A1

公开(公告)日：2025-03-06

申请号：US18242991

申请日：2023-09-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Deepak Vasant KULKARNI ,  Sri Ranga Sai BOYAPATI ,  Rajen Singh SIDHU

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/16

Abstract: Active and passive electronic components are placed on a substrate and encapsulated with mold material to produce a molded core substrate for fabricating a hybrid integrated circuit (IC) device. A carrier has a release film laminated to a face thereof. A seed layer of copper is added over the release film and fiducials are plated onto the copper seed layer for component placement using alignment marks on the fiducials. Mold material is applied to the encapsulation layer and around and over the components. Mold material is ground planar with component tops. The carrier and release film are removed, leaving the copper seed layer exposed, which is etched to a pattern. Holes are formed in the mold material and then surfaces thereof are copper plated. A multilayer dielectric film is laminated over copper plating. Vias are formed in the multilayer dielectric film for connections to components.

公开(公告)号：US20250077409A1

公开(公告)日：2025-03-06

申请号：US18240640

申请日：2023-08-31

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： Kishore Punniyamurthy ,  Richard David Sodke ,  Furkan Eris ,  Sergey Blagodurov ,  Bradford Michael Beckmann ,  Brandon Keith Potter ,  Khaled Hamidouche

IPC: G06F12/02 ,  G06F13/16

Abstract: A device includes a plurality of processing elements (PEs). A symmetric memory is allocated in each of the plurality of PEs. The device includes a switch connected to the plurality of PEs. The switch is to: receive, from a first processing element (PE) of the plurality of PEs, a message that includes a buffer offset, compute, based on the buffer offset, a first memory address of a first buffer in a first symmetric memory of the first PE and a second memory address of a second buffer in a second symmetric memory of a second PE of the plurality of PEs, and initiate, based on the first memory address and the second memory address, a direct memory access operation to access the first buffer and the second buffer.

公开(公告)号：US20250077320A1

公开(公告)日：2025-03-06

申请号：US18458571

申请日：2023-08-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Nithya Viswanathan Shyla ,  Manu Shantharam

IPC: G06F9/54

Abstract: A message passing interface processing system is described. In accordance with message passing logic, a node selects an affinity domain for communication of data associated with a message passing interface and selects a first rank of a first process of the message passing interface assigned to a first partition of the affinity domain as a first partition leader rank and an affinity domain leader rank. The node selects a second rank of a second process of the message passing interface assigned to a second partition of the affinity domain as second partition leader rank, receives the data at the first partition leader rank, and communicates the data from the first partition leader rank to the second partition leader rank.

公开(公告)号：US12243576B2

公开(公告)日：2025-03-04

申请号：US18198709

申请日：2023-05-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Jing Wang ,  Kedarnath Balakrishnan ,  Kevin M. Brandl ,  James R. Magro

IPC: G06F9/24 ,  G06F1/3203 ,  G06F9/4401 ,  G11C11/406

Abstract: A method for performing stutter of dynamic random access memory (DRAM) where a system on a chip (SOC) initiates bursts of requests to the DRAM to fill buffers to allow the DRAM to self-refresh is disclosed. The method includes issuing, by a system management unit (SMU), a ForceZQCal command to the memory controller to initiate the stutter procedure in response to receiving a timeout request, such as an SMU ZQCal timeout request, periodically issuing a power platform threshold (PPT) request, by the SMU, to the memory controller, and sending a ForceZQCal command prior to a PPT request to ensure re-training occurs after ZQ Calibration. The ForceZQCal command issued prior to PPT request may reduce the latency of the stutter. The method may further include issuing a ForceZQCal command prior to each periodic re-training.

公开(公告)号：US12237286B2

公开(公告)日：2025-02-25

申请号：US18455960

申请日：2023-08-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Rahul Agarwal

IPC: H01L23/00 ,  H01L23/528

Abstract: A semiconductor package for high-speed die connections using a conductive insert, the semiconductor package comprising: a die; a plurality of redistribution layers; a conductive insert housed in a perforation through the plurality of redistribution layers; and a conductive bump conductively coupled to an input/output (I/O) connection point of the die via the conductive insert.

公开(公告)号：US12237026B1

公开(公告)日：2025-02-25

申请号：US17982382

申请日：2022-11-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Vaibhav Anand Srivastava ,  Pankaj Kumar

IPC: G11C17/00 ,  G11C17/12 ,  G11C17/14 ,  G11C17/16

Abstract: The disclosed computer-implemented method relating to read-only memory can include (i) asserting a column select signal to select a particular column within a column mux read-only memory, (ii) forwarding, in response to asserting the column select signal, a bit value stored at that particular column to a gate of a transistor that connects a first stage local bitline to a second stage local bitline, and (iii) forwarding an inversion of the bit value to the second stage local bitline through the drain of the transistor for local bitline sensing. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US12236134B2

公开(公告)日：2025-02-25

申请号：US17953723

申请日：2022-09-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Mahzabeen Islam ,  Shaizeen Dilawarhusen Aga ,  Johnathan Robert Alsop ,  Mohamed Assem Abd ElMohsen Ibrahim ,  Nuwan S Jayasena

IPC: G06F3/06

Abstract: In accordance with the described techniques for bank-level parallelism for processing in memory, a plurality of commands are received for execution by a processing in memory component embedded in a memory. The memory includes a first bank and a second bank. The plurality of commands include a first stream of commands which cause the processing in memory component to perform operations that access the first bank and a second stream of commands which cause the processing in memory component to perform operations that access the second bank. A next row of the first bank that is to be accessed by the processing in memory component is identified. Further, a precharge command is scheduled to close a first row of the first bank and an activate command is scheduled to open the next row of the first bank in parallel with execution of the second stream of commands.

公开(公告)号：US12229570B2

公开(公告)日：2025-02-18

申请号：US17952270

申请日：2022-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Bin He ,  Michael John Mantor ,  Brian Emberling ,  Liang Huang ,  Chao Liu

IPC: G06F9/30 ,  G06F1/20 ,  G06F9/38 ,  G06F15/80

Abstract: Block data load with transpose techniques are described. In one example, an input is received, at a control unit, specifying an instruction to load a block of data to at least one memory module using a transpose operation. Responsive to the receiving the input by the control unit, the block of data is caused to be loaded to the at least one memory module by transposing the block of data to form a transposed block of data and storing the transposed block of data in the at least one memory.

公开(公告)号：US12217061B2

公开(公告)日：2025-02-04

申请号：US18309536

申请日：2023-04-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Maxim V. Kazakov

IPC: G06F9/30 ,  G06F9/38

Abstract: Techniques are provided for executing wavefronts. The techniques include at a first time for issuing instructions for execution, performing first identifying, including identifying that sufficient processing resources exist to execute a first set of instructions together within a processing lane; in response to the first identifying, executing the first set of instructions together; at a second time for issuing instructions for execution, performing second identifying, including identifying that no instructions are available for which sufficient processing resources exist for execution together within the processing lane; and in response to the second identifying, executing an instruction independently of any other instruction.

公开(公告)号：US20250037750A1

公开(公告)日：2025-01-30

申请号：US18783900

申请日：2024-07-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Indrani Paul ,  Benjamin Tsien ,  James R. Magro

IPC: G11C11/4074 ,  G11C5/14 ,  G11C11/406

Abstract: The disclosed systems and methods include a control circuit for entering a low power state of a memory by preserving a context of the memory's controller and power gating the memory's physical layer. The context can be saved to a non-volatile memory device or by keeping a retention supply voltage to a register of the memory controller. Various other methods, systems, and computer-readable media are also disclosed.