公开(公告)号：US20250079328A1

公开(公告)日：2025-03-06

申请号：US18242991

申请日：2023-09-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Deepak Vasant KULKARNI ,  Sri Ranga Sai BOYAPATI ,  Rajen Singh SIDHU

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/16

Abstract: Active and passive electronic components are placed on a substrate and encapsulated with mold material to produce a molded core substrate for fabricating a hybrid integrated circuit (IC) device. A carrier has a release film laminated to a face thereof. A seed layer of copper is added over the release film and fiducials are plated onto the copper seed layer for component placement using alignment marks on the fiducials. Mold material is applied to the encapsulation layer and around and over the components. Mold material is ground planar with component tops. The carrier and release film are removed, leaving the copper seed layer exposed, which is etched to a pattern. Holes are formed in the mold material and then surfaces thereof are copper plated. A multilayer dielectric film is laminated over copper plating. Vias are formed in the multilayer dielectric film for connections to components.

公开(公告)号：US20240404897A1

公开(公告)日：2024-12-05

申请号：US18676665

申请日：2024-05-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Deepak Vasant KULKARNI ,  Raja SWAMINATHAN ,  Mihir PANDYA ,  Liwei WANG ,  Samuel NAFFZIGER

IPC: H01L23/13 ,  H01L23/00 ,  H01L23/498 ,  H01L25/18

Abstract: A chip complex is provided that includes at least a first IC die present in a first common tier, a passive interposer, and a plurality of IC dies present in a second common tier. The passive interposer includes an interconnect formed in a back end of the line (BEOL) region. The first IC die present in the first common tier are hybrid bonded to a top side of the passive interposer. The plurality of IC dies present in the second common tier are also hybrid bonded to a bottom side of the passive interposer.

公开(公告)号：US20250079276A1

公开(公告)日：2025-03-06

申请号：US18241140

申请日：2023-08-31

Applicant: Advanced Micro Devices, Inc. ,  XILINX, INC.

Inventor： Manish DUBEY ,  Frank Peter LAMBRECHT ,  Brett P. WILKERSON ,  Deepak Vasant KULKARNI ,  Hemanth Kumar DHAVALESWARAPU ,  Priyal SHAH

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/043 ,  H01L25/065 ,  H05K1/14

Abstract: Disclosed herein is a chip package assembly that includes a package substrate coupled with an integrated circuit die, a stiffener attached to a top surface of the package substrate, and a connector assembly integrated with the stiffener. Both the connector assembly and the stiffener are disposed at a peripheral area of the top surface. The connector assembly includes a bracket and a connector. The connector is configured to connect with one or more optical cables or electrical connectors. The bracket may be formed by a cavity in the stiffener. The bracket may be attached to the top surface of the package substrate. The stiffener may be coupled with the bracket directly or via the connector. Additionally, a frame coupled to the stiffener or a PCB board may be used to secure the bracket in place.

公开(公告)号：US20240371714A1

公开(公告)日：2024-11-07

申请号：US18644958

申请日：2024-04-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Deepak Vasant KULKARNI ,  Raja SWAMINATHAN ,  Sri Ranga Sai BOYAPATI ,  Brett P. WILKERSON

IPC: H01L23/15 ,  H01L21/683 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: A chip package having a package substrate including a top surface. A first chip module and a second chip module are mounted above the top surface of the package substrate. A first interposer is disposed between the package substrate and the first and second chip modules and includes a glass interposer. The first interposer couples the first and second chip modules to the package substrate. An interconnect bridge is disposed in a cavity of the glass interposer. The interconnect bridge includes circuitry that connects a circuitry of the first chip module to a circuitry of the second chip module.

公开(公告)号：US20240234304A1

公开(公告)日：2024-07-11

申请号：US18402688

申请日：2024-01-02

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Deepak Vasant KULKARNI ,  Samuel NAFFZIGER ,  Raja SWAMINATHAN ,  Matthew STRAAYER ,  Justin Michael BURKHART ,  Sri Ranga Sai BOYAPATI ,  Hemanth Kumar DHAVALESWARAPU ,  Alexander Helmut PFEIFFENBERGER ,  Manjunath D. HARITSA

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5227 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/29 ,  H01L25/0652 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/29009 ,  H01L2224/29025 ,  H01L2924/1206 ,  H01L2924/1427 ,  H01L2924/1431 ,  H01L2924/15311

Abstract: Chip packages are described herein that includes chiplets embedded in a core of a substrate of the chip package, such as a package substrate or an interposer. In one example, the chiplet includes voltage regulation circuitry that is coupled through a substrate core embedded inductor to an integrated circuit (IC) die mounted to the substrate.