公开(公告)号：US5815714A

公开(公告)日：1998-09-29

申请号：US839229

申请日：1997-04-21

申请人： Avadhani Shridhar ,  John Simons

发明人： Avadhani Shridhar ,  John Simons

IPC分类号： G06F11/28 ,  G06F9/44 ,  G06F11/34 ,  G06F11/36 ,  G06F9/45

CPC分类号： G06F11/3624 ,  G06F8/30 ,  G06F11/3466

摘要： A method and apparatus for re-generating debug commands is provided comprising a source program having embedded debug commands in a first distinguishable field, and an assembler. The assembler operates on the source code extracting the embedded debug commands and associated address information from the source code while generating object code. The debug commands are stored in a command file for use during simulation. A simulator executes the assembled object code in conjunction with a debugger which executes the stored debug commands as designated during the execution cycle. Upon the termination of a simulation run and the subsequent modification of the source program, the debug commands are automatically re-generated with correct addresses as determined during the subsequent assembly. When the edited source file is loaded, the break-points are cleared and a new command file is executed to insure that the break-points are relocated to the correct source lines. The execution of the embedded debug commands can be enabled or disabled by means of a command line option, so when the debugging is complete, the debug information will not be outputted.

摘要翻译： 提供了一种用于重新生成调试命令的方法和装置，包括在第一可区分字段中具有嵌入式调试命令的源程序和汇编器。 汇编程序对源代码进行操作，从源代码中提取嵌入式调试命令和关联的地址信息，同时生成目标代码。 调试命令存储在命令文件中，以便在仿真期间使用。 模拟器与执行在执行周期中指定的存储的调试命令的调试器一起执行组装的目标代码。 在模拟运行结束和源程序的后续修改之后，将在随后的组装过程中确定的正确地址自动重新生成调试命令。 当编辑的源文件被加载时，断点被清除，并且执行新的命令文件以确保断点被重定位到正确的源行。 可以通过命令行选项启用或禁用嵌入式调试命令的执行，所以调试完成后，调试信息将不会被输出。

公开(公告)号：US08223859B2

公开(公告)日：2012-07-17

申请号：US12459129

申请日：2009-06-25

申请人： Sam Heidari ,  Sivannarayana Nagireddi ,  Sigurd Schelstraete ,  Avadhani Shridhar

发明人： Sam Heidari ,  Sivannarayana Nagireddi ,  Sigurd Schelstraete ,  Avadhani Shridhar

IPC分类号： H04K1/10 ,  H04L27/28

CPC分类号： H04B3/542 ,  H04B2203/5408 ,  H04B2203/5445 ,  H04B2203/5454 ,  H04L5/0037 ,  H04L5/0064 ,  H04L5/0092 ,  H04L5/1438

摘要： A multi-tone modem with shared and discrete components forming a transmit path and a receive path configured to couple to a wired communication medium to communicate at least one multi-tone modulated communication channel thereon. The modem includes a multi-tone modulator component and a configurable frequency up converter component. The multi-tone modulator component is configured for multi-tone modulation and demodulation of a transmitted and received communication channel at a base band frequency range. The configurable frequency up converter component is coupled to the multi-tone modulator to selectably up convert the frequency range of the transmitted base band signal from the multi-tone modulator to that of a selected communication band and down convert received signals from the selected communication band to the base band for demodulation by the multi-tone modulator.

摘要翻译： 具有形成发送路径的共享和分立组件的多音调制解调器和被配置为耦合到有线通信介质以在其上通信至少一个多音调调制通信信道的接收路径。 调制解调器包括多音调制器组件和可配置的升频转换器组件。 多音调制器部件被配置为在基带频率范围内对发送和接收的通信信道进行多音调制和解调。 可配置的上变频器组件耦合到多音调制器以可选择地将来自多音调制器的发射基带信号的频率范围转换成所选择的通信频带的频率范围，并且将来自所选择的通信频带的接收信号 到基带以进行多音调制器的解调。

公开(公告)号：US07881362B2

公开(公告)日：2011-02-01

申请号：US11901346

申请日：2007-09-15

申请人： Avadhani Shridhar ,  Sam Heidari ,  Rouben Toumani ,  Ying Wu

发明人： Avadhani Shridhar ,  Sam Heidari ,  Rouben Toumani ,  Ying Wu

IPC分类号： H04B1/38

CPC分类号： H04L5/006 ,  H04L5/0042 ,  H04L5/0046

摘要： A multi-tone transceiver including: a channel controller and a plurality of components forming a transmit path and a receive path. The channel controller configured to determine bit-loading for each successive symbol or tone set based on a 1st noise margin target for a first subset of tones in each tone set dedicated to transport of a robust communications channel (RCC) and based on a 2nd noise margin target less than the 1st noise margin target for remaining tones in each tone set dedicated to a standard communications channel (SCC). The plurality of components forming the transmit and receive paths are responsive to the channel controller to select for data modulated on a given tone at least one of smaller constellations and higher gain scaling levels when the given tone corresponds to an RCC tone as compared to an SCC tone, whereby the first set of tones dedicated to the RCC exhibit greater immunity to noise variations than the remaining tones dedicated to the SCC.

摘要翻译： 一种多音调收发器，包括：信道控制器和形成发送路径和接收路径的多个组件。 所述信道控制器被配置为基于专用于传输鲁棒通信信道（RCC）的每个音调集合中的第一音调子集的第一噪声容限目标以及基于第二噪声来确定每个连续符号或音调集合的比特加载 余量目标小于专用于标准通信信道（SCC）的每个音调集合中的剩余音调的第一噪声容限度目标。 形成发送和接收路径的多个组件响应于信道控制器，以便在给定音调对应于RCC音调与SCC相比时，为给定音调调制的数据中的至少一个较小星座和较高增益缩放级别 音调，由此专用于RCC的第一组音调比专用于SCC的剩余音调具有更大的对噪声变化的抗扰度。

公开(公告)号：US07028063B1

公开(公告)日：2006-04-11

申请号：US09698824

申请日：2000-10-26

申请人： Omprakash S. Sarmaru ,  Raminder S. Bajwa ,  Sridhar Begur ,  Avadhani Shridhar ,  Sam Heid Ari ,  Behrooz Rezvani

发明人： Omprakash S. Sarmaru ,  Raminder S. Bajwa ,  Sridhar Begur ,  Avadhani Shridhar ,  Sam Heid Ari ,  Behrooz Rezvani

IPC分类号： F06F17/14

CPC分类号： G06F17/141 ,  H04L27/2628 ,  H04L27/265

摘要： A Fourier transform processor utilizing discrete circuits each of which is configurable for processing a wide range of sample sizes. A single pipeline supports multiplexed bi-directional transformations between for example the time and frequency domains. In an embodiment of the invention the Fourier Transform processor may be implemented as part of a digital signal processor (DSP). In this embodiment the DSP may implement both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session.

摘要翻译： 利用离散电路的傅里叶变换处理器，每个离散电路可配置用于处理各种样本大小的范围。 单个流水线支持例如时域和频域之间的复用双向变换。 在本发明的实施例中，傅里叶变换处理器可以被实现为数字信号处理器（DSP）的一部分。 在该实施例中，DSP可以在宽范围的样本大小和X-DSL协议上实现离散傅里叶变换（DFT）和离散傅里叶逆变换（IDFT）两者。 每个具有不同的X-DSL协议的多个信道可以在同一个会话中处理。

公开(公告)号：US5880981A

公开(公告)日：1999-03-09

申请号：US695617

申请日：1996-08-12

申请人： Hirotsugu Kojima ,  Avadhani Shridhar

发明人： Hirotsugu Kojima ,  Avadhani Shridhar

IPC分类号： G06F7/00 ,  G06F7/544 ,  G06F9/305 ,  G06F7/38 ,  G06F7/52

CPC分类号： G06F7/5443

摘要： The present invention contemplates an improved multiplier circuit and method for reducing power consumption by reducing the number of transitions to the input of the multiplier. Each input to the multiplier is fixed for as long as possible by reordering the sequence of the multiplications to take advantage of duplicate input values. The intermediate results of each multiplication are stored in separate accumulators to obtain the final resultants. Power consumption is further reduced through a reduction in the number of transitions on the data bus linking the multiplier and the data register file containing the accumulators.

摘要翻译： 本发明考虑了改进的乘法器电路和方法，用于通过减少向乘法器的输入的转换次数来降低功耗。 通过重新排序乘法序列以利用重复输入值，乘法器的每个输入被固定为尽可能长的时间。 每个乘法的中间结果存储在单独的累加器中以获得最终的结果。 通过减少连接乘法器和包含累加器的数据寄存器文件的数据总线上的转换次数，能够进一步降低功耗。

公开(公告)号：US5381360A

公开(公告)日：1995-01-10

申请号：US127431

申请日：1993-09-27

申请人： Avadhani Shridhar ,  Douglas J. Gorny

发明人： Avadhani Shridhar ,  Douglas J. Gorny

IPC分类号： G06F12/02 ,  G06F5/10 ,  G06F9/355 ,  G06F7/72

CPC分类号： G06F5/10 ,  G06F9/3552 ,  G06F2205/106

摘要： A modulo addition circuit generates a sequence of values within a specified range having a lower bound value and an upper bound value. The modulo addition circuit generates a first value by adding a displacement value to a previously defined starting value, and generates a second value by adding to or subtracting from the first generated value a modulo value. Both the first and second values are generated in a single computational cycle using a single address circuit. When the first generated value is in the range defined the lower bound and upper bound values, the modulo addition circuit outputs the first value; otherwise the modulo addition circuit outputs the second generated value. The value output by the modulo addition circuit is stored in a register so as to be available as the starting value in a next computational cycle.

摘要翻译： 模加法电路产生具有下限值和上限值的指定范围内的值序列。 模加法电路通过将位移值加到先前定义的起始值来产生第一值，并且通过将第一生成值加到或减去模值来产生第二值。 第一和第二值都是使用单个地址电路在单个计算周期内生成的。 当第一生成值在限定下限界限值和上限值的范围内时，模加法电路输出第一值; 否则模加法电路输出第二个产生的值。 由模加法电路输出的值存储在寄存器中，以便在下一个计算循环中可用作起始值。

公开(公告)号：US09065534B2

公开(公告)日：2015-06-23

申请号：US13403956

申请日：2012-02-23

申请人： Avadhani Shridhar ,  Kevin Fisher

发明人： Avadhani Shridhar ,  Kevin Fisher

IPC分类号： H04B3/32

CPC分类号： H04B3/32 ,  H04B3/487 ,  H04M11/062

摘要： A DSL system performs crosstalk cancellation using a plurality of vectoring cancellation chips that are partitioned into two or more groups based on DSL victim lines or DSL disturber lines or DSL tones. Embodiments of the invention include both single-criteria and double-criteria partitioning methods. In double-criteria embodiments, the vectoring cancellation VCE chips are first partitioned into two or more victim DSL line groups and then in each group the VCE chips are further partitioned by disturber DSL line processing. Alternately, the vectoring cancellation VCE chips are first partitioned into two or more disturber DSL line groups and then within each group further partitioned by victim DSL line processing. By partitioning the computation as described herein, the invention reduces the bandwidth and the number of links between the chips, without too much co-ordination complexity. This allows crosstalk cancellation across larger vectored groups.

摘要翻译： DSL系统使用基于DSL受害线或DSL干扰线或DSL音调将其划分为两个或多个组的多个向量消除芯片来执行串扰消除。 本发明的实施例包括单一标准和双准则划分方法。 在双标准实施例中，向量消除VCE码片首先划分成两个或多个受害DSL线路组，然后在每个组中，VCE码片进一步被干扰DSL线路处理分割。 或者，矢量取消VCE芯片首先划分成两个或更多个干扰DSL线路组，然后在每个组内进一步被受害DSL线路处理划分。 通过如本文所述分割计算，本发明降低了芯片之间的带宽和链路数量，而没有太多的协调复杂性。 这允许跨较大矢量组的串扰消除。

公开(公告)号：US07406042B1

公开(公告)日：2008-07-29

申请号：US10290973

申请日：2002-11-07

申请人： Avadhani Shridhar ,  Behrooz Rezvani ,  Sushil Agarwal ,  Alfred Mui ,  Masoud Eskandari

发明人： Avadhani Shridhar ,  Behrooz Rezvani ,  Sushil Agarwal ,  Alfred Mui ,  Masoud Eskandari

IPC分类号： H04L12/26 ,  H04L12/28 ,  H04J1/00

CPC分类号： H04L43/0852 ,  H04L12/2856 ,  H04L12/2885 ,  H04L12/2898 ,  H04L41/0896 ,  H04L41/5003 ,  H04L41/5025 ,  H04L41/5067

摘要： A bundler, un-bundler and sequencer for use in controlling and driving opposing sets of logical or physical modems to drive multiple-subscriber lines with multiple communication channels. The sequencer determines subscriber requirements such as maximum and minimum bandwidth and quality of service. The sequencer also determines bandwidth availability and status of multiple subscriber lines from which a bundle may be formed. The bundler couple to the sequencer and implement header or headerless insertion of multiple channels in round robin sequence into the X-DSL frames at data rates which correspond with subscriber requirements. The un-bundler reverses the process of the bundler and passes the appropriate packet data onto the corresponding network.

摘要翻译： 捆绑器，非捆绑器和定序器，用于控制和驱动相对的逻辑或物理调制解调器组，以驱动具有多个通信信道的多用户线路。 定序器确定用户需求，如最大和最小带宽以及服务质量。 定序器还确定可以形成束的多个用户线的带宽可用性和状态。 捆绑器耦合到定序器，并以符合用户要求的数据速率将轮询序列中的多个信道的头部或无头插入多个信道插入到X-DSL帧中。 解包器反转捆绑器的过程，并将适当的分组数据传递到相应的网络上。

公开(公告)号：US20080069193A1

公开(公告)日：2008-03-20

申请号：US11901346

申请日：2007-09-15

申请人： Avadhani Shridhar ,  Sam Heidari ,  Rouben Toumani ,  Ying Wu

发明人： Avadhani Shridhar ,  Sam Heidari ,  Rouben Toumani ,  Ying Wu

IPC分类号： H04B1/38

CPC分类号： H04L5/006 ,  H04L5/0042 ,  H04L5/0046

摘要： A multi-tone transceiver including: a channel controller and a plurality of components forming a transmit path and a receive path. The channel controller configured to determine bit-loading for each successive symbol or tone set based on a 1st noise margin target for a first subset of tones in each tone set dedicated to transport of a robust communications channel (RCC) and based on a 2nd noise margin target less than the 1st noise margin target for remaining tones in each tone set dedicated to a standard communications channel (SCC). The plurality of components forming the transmit and receive paths are responsive to the channel controller to select for data modulated on a given tone at least one of smaller constellations and higher gain scaling levels when the given tone corresponds to an RCC tone as compared to an SCC tone, whereby the first set of tones dedicated to the RCC exhibit greater immunity to noise variations than the remaining tones dedicated to the SCC.

摘要翻译： 一种多音调收发器，包括：信道控制器和形成发送路径和接收路径的多个组件。 信道控制器，被配置为基于专用于传输鲁棒通信信道的每个音调集合中的第一音调子集，确定每个连续符号或音调集合的比特加载（...） RCC），并且基于小于专用于标准通信信道（SCC）的每个音调集合中的剩余音调的小于噪声余量目标的2 nd nd噪声容限目标。 形成发送和接收路径的多个组件响应于信道控制器，以便在给定音调对应于RCC音调与SCC相比时，为给定音调调制的数据中的至少一个较小星座和较高增益缩放级别 音调，由此专用于RCC的第一组音调比专用于SCC的剩余音调具有更大的对噪声变化的抗扰度。

公开(公告)号：US06842429B1

公开(公告)日：2005-01-11

申请号：US09776066

申请日：2001-02-02

申请人： Avadhani Shridhar ,  T. R. Ramesh ,  Raminder S. Bajwa ,  Masoud Eskandari ,  Firooz Massoudi ,  Omprakash S. Sarmaru ,  Behrooz Rezvani

发明人： Avadhani Shridhar ,  T. R. Ramesh ,  Raminder S. Bajwa ,  Masoud Eskandari ,  Firooz Massoudi ,  Omprakash S. Sarmaru ,  Behrooz Rezvani

IPC分类号： H04L12/26 ,  H04L12/66

CPC分类号： H04L12/66

摘要： The current invention provides a digital signal processor which supports multiple X-DSL protocols and a multiplicity of channels on a single chip. Each channel is packetized and each packet includes control information for controlling the performance of the components/modules on the transmit and receive path. Further flexibility is derived from an architecture which incorporates discrete and shared modules on the transmit path and the receive path. The transmit path and receive path modules are collectively controlled by control information in selected ones of the packets and operate on each channel's packets at an appropriate rate, and protocol for the channel. A digital signal processor (DSP) is disclosed which incorporates these features. The DSP exhibits a favorable form factor, and flexibility as to protocols and line codes, and numbers of channels supported.

摘要翻译： 本发明提供了在单个芯片上支持多个X-DSL协议和多个信道的数字信号处理器。 每个信道被分组化，并且每个分组包括用于控制发送和接收路径上的组件/模块的性能的控制信息。 来自在发送路径和接收路径上包含离散和共享模块的架构的进一步的灵活性。 发送路径和接收路径模块由选择的分组中的控制信息共同控制，并以适当的速率对每个信道的分组进行操作，以及针对该信道的协议。 公开了一种包含这些特征的数字信号处理器（DSP）。 DSP具有良好的外形尺寸，对协议和线路代码的灵活性以及支持的通道数量。