公开(公告)号：US20130051488A1

公开(公告)日：2013-02-28

申请号：US13403956

申请日：2012-02-23

申请人： Avadhani Shridhar ,  Kevin Fisher

发明人： Avadhani Shridhar ,  Kevin Fisher

IPC分类号： H04B15/00

CPC分类号： H04B3/32 ,  H04B3/487 ,  H04M11/062

摘要： A DSL system performs crosstalk cancellation using a plurality of vectoring cancellation chips that are partitioned into two or more groups based on DSL victim lines or DSL disturber lines or DSL tones. Embodiments of the invention include both single-criteria and double-criteria partitioning methods. In double-criteria embodiments, the vectoring cancellation VCE chips are first partitioned into two or more victim DSL line groups and then in each group the VCE chips are further partitioned by disturber DSL line processing. Alternately, the vectoring cancellation VCE chips are first partitioned into two or more disturber DSL line groups and then within each group further partitioned by victim DSL line processing. By partitioning the computation as described herein, the invention reduces the bandwidth and the number of links between the chips, without too much co-ordination complexity. This allows crosstalk cancellation across larger vectored groups.

摘要翻译： DSL系统使用基于DSL受害线或DSL干扰线或DSL音调将其划分为两个或多个组的多个向量消除芯片来执行串扰消除。 本发明的实施例包括单一标准和双准则划分方法。 在双标准实施例中，向量消除VCE码片首先划分成两个或多个受害DSL线路组，然后在每个组中，VCE码片进一步被干扰DSL线路处理分割。 或者，矢量取消VCE芯片首先划分成两个或更多个干扰DSL线路组，然后在每个组内进一步被受害DSL线路处理划分。 通过如本文所述分割计算，本发明降低了芯片之间的带宽和链路数量，而没有太多的协调复杂性。 这允许跨较大矢量组的串扰消除。

公开(公告)号：US09065534B2

公开(公告)日：2015-06-23

申请号：US13403956

申请日：2012-02-23

申请人： Avadhani Shridhar ,  Kevin Fisher

发明人： Avadhani Shridhar ,  Kevin Fisher

IPC分类号： H04B3/32

CPC分类号： H04B3/32 ,  H04B3/487 ,  H04M11/062

摘要： A DSL system performs crosstalk cancellation using a plurality of vectoring cancellation chips that are partitioned into two or more groups based on DSL victim lines or DSL disturber lines or DSL tones. Embodiments of the invention include both single-criteria and double-criteria partitioning methods. In double-criteria embodiments, the vectoring cancellation VCE chips are first partitioned into two or more victim DSL line groups and then in each group the VCE chips are further partitioned by disturber DSL line processing. Alternately, the vectoring cancellation VCE chips are first partitioned into two or more disturber DSL line groups and then within each group further partitioned by victim DSL line processing. By partitioning the computation as described herein, the invention reduces the bandwidth and the number of links between the chips, without too much co-ordination complexity. This allows crosstalk cancellation across larger vectored groups.

摘要翻译： DSL系统使用基于DSL受害线或DSL干扰线或DSL音调将其划分为两个或多个组的多个向量消除芯片来执行串扰消除。 本发明的实施例包括单一标准和双准则划分方法。 在双标准实施例中，向量消除VCE码片首先划分成两个或多个受害DSL线路组，然后在每个组中，VCE码片进一步被干扰DSL线路处理分割。 或者，矢量取消VCE芯片首先划分成两个或更多个干扰DSL线路组，然后在每个组内进一步被受害DSL线路处理划分。 通过如本文所述分割计算，本发明降低了芯片之间的带宽和链路数量，而没有太多的协调复杂性。 这允许跨较大矢量组的串扰消除。

公开(公告)号：US06366937B1

公开(公告)日：2002-04-02

申请号：US09267899

申请日：1999-03-11

申请人： Avadhani Shridhar ,  Arindam Saha

发明人： Avadhani Shridhar ,  Arindam Saha

IPC分类号： G06F1714

CPC分类号： G06F9/30014 ,  G06F9/30036 ,  G06F17/142

摘要： A system and method that implement a butterfly operation for a fast fourier transform operation in a processor using a matrix-vector-multiply instruction. A first set of inputs to the butterfly operation are defined as r1+j i1 and r2+j i2, and a twiddle factor Wn is defined as Wn=e−j2&pgr;/N=cos(2&pgr;/N)−j sin(2&pgr;/N)=a+jb. The butterfly operation stores r1, i1, r2 and i2 in a first set of registers and stores the twiddle factor in matrix registers. The matrix-vector-multiply instruction is executed between the matrix registers and the first set of registers.

摘要翻译： 一种在使用矩阵向量乘法指令的处理器中实现用于快速傅里叶变换操作的蝶形运算的系统和方法。 蝶形运算的第一组输入被定义为r1 + ji1和r2 + j i2，旋转因子Wn定义为Wn = e-j2pi / N = cos（2pi / N）-jsin（2pi / N）= a + jb。 蝶形运算将r1，i1，r2和i2存储在第一组寄存器中，并将旋转因子存储在矩阵寄存器中。 矩阵向量乘法指令在矩阵寄存器和第一组寄存器之间执行。

公开(公告)号：US07315571B1

公开(公告)日：2008-01-01

申请号：US09837914

申请日：2001-04-18

申请人： Sam Heidari ,  Behrooz Rezvani ,  Raminder S. Bajwa ,  Jacky Chow ,  Avadhani Shridhar ,  Dale Smith ,  John Gevargiz ,  Saman Behtash

发明人： Sam Heidari ,  Behrooz Rezvani ,  Raminder S. Bajwa ,  Jacky Chow ,  Avadhani Shridhar ,  Dale Smith ,  John Gevargiz ,  Saman Behtash

IPC分类号： H04B1/38

CPC分类号： H04L27/2628 ,  H04L5/0042 ,  H04L5/0044 ,  H04L5/0064 ,  H04L27/0002 ,  H04L27/265 ,  H04M11/062

摘要： A transceiver for communicating a multi-tone modulated communication channel on a subscriber line. The transceiver includes: a digital signal processor (DSP) with a Fourier transform module and an analog front end (AFE). The DSP determines an available range of frequencies on the subscriber line and expands or contracts the tone spacing of each of a fixed number “N” of tones accordingly by decreasing or increasing the processing interval associated with the Fourier transform of each tone set. The AFE performs digital-to-analog conversion of the multi-tone modulated communication channel at rates compatible with the processing interval of the Fourier transform module; whereby the range of frequencies spanned by the modulated tones on the subscriber line conforms to the available of frequencies on the subscriber line.

摘要翻译： 用于在用户线路上传送多音调调制通信信道的收发器。 收发器包括：具有傅立叶变换模块和模拟前端（AFE）的数字信号处理器（DSP）。 DSP确定用户线路上的可用频率范围，并通过减少或增加与每个音调集合的傅里叶变换相关联的处理间隔来相应地扩展或收缩固定数量“N”个音调中的每一个的音调间隔。 AFE以与傅里叶变换模块的处理间隔兼容的速率执行多音调调制通信信道的数模转换; 由此用户线路上的调制音调跨越的频率范围符合用户线上的可用频率。

公开(公告)号：US06940807B1

公开(公告)日：2005-09-06

申请号：US09699193

申请日：2000-10-26

申请人： Behrooz Rezvani ,  Avadhani Shridhar ,  Raminder S. Bajwa ,  Tiruvur R. Ramesh ,  Masoud Eskandari ,  Firooz Massoudi ,  Sam Heidari ,  Omprakash S. Sarmaru ,  Sridhar Begur

发明人： Behrooz Rezvani ,  Avadhani Shridhar ,  Raminder S. Bajwa ,  Tiruvur R. Ramesh ,  Masoud Eskandari ,  Firooz Massoudi ,  Sam Heidari ,  Omprakash S. Sarmaru ,  Sridhar Begur

IPC分类号： H04J11/00

CPC分类号： G06F17/142 ,  H04L27/2628 ,  H04L27/265

摘要： The current invention provides a DSP which accommodates multiple current X-DSL protocols and is further configurable to support future protocols. The DSP is implemented with shared and dedicated hardware components on both the transmit and receive paths. The DSP implements both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) portions across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session. The DSP offers the speed associated with hardware implementation of the transforms and the flexibility of a software only implementation. Traffic flow is regulated in the chip using a packet based schema in which each packet is associated with a specific channel of upstream and downstream data. Header and control information in each packet is used to govern the processing of each packet as it moves along either the transmit path or receive path. The DSP of the current invention may advantageously be utilized in fields other than communications, such as: medical and other imaging, seismic analysis, radar and other military applications, pattern recognition, signal processing etc. The present invention provides a signal processing architecture that supports scalability of CO/DLC/ONU resources, and allows a significantly more flexible hardware response to the evolving X-DSL standards without over committing of hardware resources. As standards evolve hardware may be reconfigured to support the new standards.

摘要翻译： 本发明提供一种DSP，其容纳多个当前的X-DSL协议，并且可进一步配置以支持未来的协议。 DSP在传输和接收路径上都具有共享和专用硬件组件。 DSP在宽范围的采样大小和X-DSL协议上实现离散傅立叶变换（DFT）和离散傅立叶逆变换（IDFT）部分。 每个具有不同的X-DSL协议的多个信道可以在同一个会话中处理。 DSP提供与转换的硬件实现相关的速度和仅用于软件的实现的灵活性。 使用基于分组的模式在芯片中调整流量流，其中每个分组与上游和下游数据的特定信道相关联。 每个数据包中的报头和控制信息用于控制每个数据包沿着发送路径或接收路径移动时的处理。 本发明的DSP可有利地用于通信以外的领域，例如：医疗和其他成像，地震分析，雷达和其他军事应用，模式识别，信号处理等。本发明提供一种信号处理架构，其支持 CO / DLC / ONU资源的可扩展性，并且允许对演进的X-DSL标准的显着更灵活的硬件响应，而不必超过硬件资源。 随着标准的发展，硬件可能被重新配置以支持新的标准。

公开(公告)号：US5727194A

公开(公告)日：1998-03-10

申请号：US478438

申请日：1995-06-07

申请人： Avadhani Shridhar ,  Kenichi Nitta

发明人： Avadhani Shridhar ,  Kenichi Nitta

IPC分类号： G06F9/32 ,  G06F9/45 ,  G06F9/30

CPC分类号： G06F8/447 ,  G06F9/325

摘要： A repeat-bit based system and method for executing zero overhead loops, or repeat loops, in an information processing chip that does not require a repeat end register or a dedicated comparator. Executing repeat loops requires a processor to iterate N times a code fragment of loop instructions. All systems providing this capability must know when to refetch the first loop instruction at the end of a repeat. To do this, the present invention adds a repeat bit to the processor's instruction set. This bit is set by the assembler/compiler that generates the executable code fragment comprising the repeat loop. Where the repeat loop includes plural instructions, the assembler sets the repeat bit of the penultimate loop instruction. As each loop instruction is fetched, decoded and executed, the decoder detects the repeat bit and passes it to loop control circuitry. If the code fragment has not been iterated N times and the repeat bit is set, the program counter (PC) is loaded with the address of the first repeat loop instruction, which is refetched. Otherwise, the PC is incremented and the next instruction is fetched. Where the repeat loop has a single instruction, a nop instruction must be added after the instruction to be repeated. Two systems and methods for maintaining the repeat count are disclosed. The first requires a decrementor that decrements the repeat count from N each time the loop is iterated. Another replaces the decrementor with the PC incrementor, which increments the repeat counter from -N or -(N-1).

摘要翻译： 一种基于重复位的系统和方法，用于在不需要重复结束寄存器或专用比较器的信息处理芯片中执行零开销环路或重复循环。 执行重复循环需要处理器重复N次循环指令的代码片段。 提供此功能的所有系统必须知道在重复结束时何时重新获取第一个循环指令。 为此，本发明向处理器的指令集添加重复位。 该位由汇编器/编译器设置，生成包含重复循环的可执行代码段。 在重复循环包括多个指令的地方，汇编器设置倒数第二个循环指令的重复位。 当每个循环指令被取出，解码和执行时，解码器检测重复位并将其传递给环路控制电路。 如果代码片段没有被迭代N次并且重复位被设置，则程序计数器（PC）被加载有第一个重复循环指令的地址，这被重写。 否则，PC将递增，并取下一条指令。 在重复循环具有单个指令的情况下，必须在要重复的指令之后添加nop指令。 公开了用于维持重复计数的两种系统和方法。 第一个需要一个递减器，每次迭代循环时，从N减少重复计数。 另一个用PC增量器代替递减器，该增量器从-N或 - （N-1）增加重复计数器。

公开(公告)号：US08223859B2

公开(公告)日：2012-07-17

申请号：US12459129

申请日：2009-06-25

申请人： Sam Heidari ,  Sivannarayana Nagireddi ,  Sigurd Schelstraete ,  Avadhani Shridhar

发明人： Sam Heidari ,  Sivannarayana Nagireddi ,  Sigurd Schelstraete ,  Avadhani Shridhar

IPC分类号： H04K1/10 ,  H04L27/28

CPC分类号： H04B3/542 ,  H04B2203/5408 ,  H04B2203/5445 ,  H04B2203/5454 ,  H04L5/0037 ,  H04L5/0064 ,  H04L5/0092 ,  H04L5/1438

摘要： A multi-tone modem with shared and discrete components forming a transmit path and a receive path configured to couple to a wired communication medium to communicate at least one multi-tone modulated communication channel thereon. The modem includes a multi-tone modulator component and a configurable frequency up converter component. The multi-tone modulator component is configured for multi-tone modulation and demodulation of a transmitted and received communication channel at a base band frequency range. The configurable frequency up converter component is coupled to the multi-tone modulator to selectably up convert the frequency range of the transmitted base band signal from the multi-tone modulator to that of a selected communication band and down convert received signals from the selected communication band to the base band for demodulation by the multi-tone modulator.

摘要翻译： 具有形成发送路径的共享和分立组件的多音调制解调器和被配置为耦合到有线通信介质以在其上通信至少一个多音调调制通信信道的接收路径。 调制解调器包括多音调制器组件和可配置的升频转换器组件。 多音调制器部件被配置为在基带频率范围内对发送和接收的通信信道进行多音调制和解调。 可配置的上变频器组件耦合到多音调制器以可选择地将来自多音调制器的发射基带信号的频率范围转换成所选择的通信频带的频率范围，并且将来自所选择的通信频带的接收信号 到基带以进行多音调制器的解调。

公开(公告)号：US07881362B2

公开(公告)日：2011-02-01

申请号：US11901346

申请日：2007-09-15

申请人： Avadhani Shridhar ,  Sam Heidari ,  Rouben Toumani ,  Ying Wu

发明人： Avadhani Shridhar ,  Sam Heidari ,  Rouben Toumani ,  Ying Wu

IPC分类号： H04B1/38

CPC分类号： H04L5/006 ,  H04L5/0042 ,  H04L5/0046

摘要： A multi-tone transceiver including: a channel controller and a plurality of components forming a transmit path and a receive path. The channel controller configured to determine bit-loading for each successive symbol or tone set based on a 1st noise margin target for a first subset of tones in each tone set dedicated to transport of a robust communications channel (RCC) and based on a 2nd noise margin target less than the 1st noise margin target for remaining tones in each tone set dedicated to a standard communications channel (SCC). The plurality of components forming the transmit and receive paths are responsive to the channel controller to select for data modulated on a given tone at least one of smaller constellations and higher gain scaling levels when the given tone corresponds to an RCC tone as compared to an SCC tone, whereby the first set of tones dedicated to the RCC exhibit greater immunity to noise variations than the remaining tones dedicated to the SCC.

摘要翻译： 一种多音调收发器，包括：信道控制器和形成发送路径和接收路径的多个组件。 所述信道控制器被配置为基于专用于传输鲁棒通信信道（RCC）的每个音调集合中的第一音调子集的第一噪声容限目标以及基于第二噪声来确定每个连续符号或音调集合的比特加载 余量目标小于专用于标准通信信道（SCC）的每个音调集合中的剩余音调的第一噪声容限度目标。 形成发送和接收路径的多个组件响应于信道控制器，以便在给定音调对应于RCC音调与SCC相比时，为给定音调调制的数据中的至少一个较小星座和较高增益缩放级别 音调，由此专用于RCC的第一组音调比专用于SCC的剩余音调具有更大的对噪声变化的抗扰度。

公开(公告)号：US07028063B1

公开(公告)日：2006-04-11

申请号：US09698824

申请日：2000-10-26

申请人： Omprakash S. Sarmaru ,  Raminder S. Bajwa ,  Sridhar Begur ,  Avadhani Shridhar ,  Sam Heid Ari ,  Behrooz Rezvani

发明人： Omprakash S. Sarmaru ,  Raminder S. Bajwa ,  Sridhar Begur ,  Avadhani Shridhar ,  Sam Heid Ari ,  Behrooz Rezvani

IPC分类号： F06F17/14

CPC分类号： G06F17/141 ,  H04L27/2628 ,  H04L27/265

摘要： A Fourier transform processor utilizing discrete circuits each of which is configurable for processing a wide range of sample sizes. A single pipeline supports multiplexed bi-directional transformations between for example the time and frequency domains. In an embodiment of the invention the Fourier Transform processor may be implemented as part of a digital signal processor (DSP). In this embodiment the DSP may implement both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session.

摘要翻译： 利用离散电路的傅里叶变换处理器，每个离散电路可配置用于处理各种样本大小的范围。 单个流水线支持例如时域和频域之间的复用双向变换。 在本发明的实施例中，傅里叶变换处理器可以被实现为数字信号处理器（DSP）的一部分。 在该实施例中，DSP可以在宽范围的样本大小和X-DSL协议上实现离散傅里叶变换（DFT）和离散傅里叶逆变换（IDFT）两者。 每个具有不同的X-DSL协议的多个信道可以在同一个会话中处理。

公开(公告)号：US5880981A

公开(公告)日：1999-03-09

申请号：US695617

申请日：1996-08-12

申请人： Hirotsugu Kojima ,  Avadhani Shridhar

发明人： Hirotsugu Kojima ,  Avadhani Shridhar

IPC分类号： G06F7/00 ,  G06F7/544 ,  G06F9/305 ,  G06F7/38 ,  G06F7/52

CPC分类号： G06F7/5443

摘要： The present invention contemplates an improved multiplier circuit and method for reducing power consumption by reducing the number of transitions to the input of the multiplier. Each input to the multiplier is fixed for as long as possible by reordering the sequence of the multiplications to take advantage of duplicate input values. The intermediate results of each multiplication are stored in separate accumulators to obtain the final resultants. Power consumption is further reduced through a reduction in the number of transitions on the data bus linking the multiplier and the data register file containing the accumulators.

摘要翻译： 本发明考虑了改进的乘法器电路和方法，用于通过减少向乘法器的输入的转换次数来降低功耗。 通过重新排序乘法序列以利用重复输入值，乘法器的每个输入被固定为尽可能长的时间。 每个乘法的中间结果存储在单独的累加器中以获得最终的结果。 通过减少连接乘法器和包含累加器的数据寄存器文件的数据总线上的转换次数，能够进一步降低功耗。