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    Hardware implementation of inverse scan for a plurality of standards
    13.
    发明申请
    Hardware implementation of inverse scan for a plurality of standards 审中-公开
    多个标准的逆扫描的硬件实现

    公开(公告)号：US20060222247A1

    公开(公告)日：2006-10-05

    申请号：US11096604

    申请日：2005-04-01

    Applicant: Bhaskar Sherigar ,  Anand Tongle

    Inventor： Bhaskar Sherigar ,  Anand Tongle

    IPC: G06K9/36

    CPC classification number: H04N19/42 ,  H04N19/12 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61

    Abstract: Presented herein are hardware implementations for inverse scanning for a plurality of standards. In one embodiment, there is presented a system for decoding video data. The system comprises an inverse scanner for inverse scanning video data encoded in accordance with a first encoding standard and for inverse scanning video data encoded in accordance with a second encoding standard. In another embodiment, there is presented a decoder for decoding video data. The decoder comprises an inverse scanner. The inverse scanner is operable to inverse scan video data encoded in accordance with a first encoding standard and inverse scan video data encoded in accordance with a second encoding standard.

    Abstract translation: 这里提出了用于多个标准的反向扫描的硬件实现。 在一个实施例中，提出了一种用于解码视频数据的系统。 该系统包括用于根据第一编码标准编码的逆扫描视频数据的逆扫描器，以及用于根据第二编码标准编码的反向扫描视频数据。 在另一实施例中，提供了一种用于对视频数据进行解码的解码器。 解码器包括逆扫描器。 逆扫描器可操作以对根据第一编码标准编码的视频数据进行逆扫描，并根据第二编码标准反编码扫描视频数据。

    Unified decoder architecture
    14.
    发明申请
    Unified decoder architecture 有权
    统一的解码器架构

    公开(公告)号：US20050175106A1

    公开(公告)日：2005-08-11

    申请号：US10775652

    申请日：2004-02-09

    Applicant: Ravindra Bidnur ,  Ramadas Pai ,  Bhaskar Sherigar ,  Aniruddha Sane ,  Sandeep Bhatia ,  Gaurav Agarwal

    Inventor： Ravindra Bidnur ,  Ramadas Pai ,  Bhaskar Sherigar ,  Aniruddha Sane ,  Sandeep Bhatia ,  Gaurav Agarwal

    IPC: G06F9/38 ,  H04N7/26 ,  H04N7/50 ,  H04N7/12

    CPC classification number: H04N19/44 ,  H04N19/61 ,  H04N19/70

    Abstract: Presented herein is a unified decoder architecture. A system comprises a video decoder, instruction memory, and a host processor. The video decoder decodes the video data encoded with the particular standard. The instruction memory stores a first set of instructions and a second set of instructions. The first set of instructions are for decoding encoded video data according to a first encoding standard. The second set of instruction are for decoding encoded video data according to a second encoding standard. The host processor provides an indication to the video decoder indicating the particular encoding standard. The video decoder executes the first set of instructions if the indication indicates that the particular encoding standard is the first encoding standard and executes the second set of instructions if the indication indicates that the particular encoding standard is the second encoding standard.

    Abstract translation: 这里呈现的是统一的解码器架构。 系统包括视频解码器，指令存储器和主机处理器。 视频解码器解码用特定标准编码的视频数据。 指令存储器存储第一组指令和第二组指令。 第一组指令用于根据第一编码标准对编码的视频数据进行解码。 第二组指令用于根据第二编码标准对编码的视频数据进行解码。 主机处理器向视频解码器提供指示特定编码标准的指示。 如果指示指示特定编码标准是第一编码标准，则视频解码器执行第一组指令，并且如果指示指示特定编码标准是第二编码标准，则执行第二组指令。

    Hardware implementation of optimized single inverse quantization engine for a plurality of standards
    16.
    发明授权
    Hardware implementation of optimized single inverse quantization engine for a plurality of standards 有权
    用于多个标准的优化的单反量子化引擎的硬件实现

    公开(公告)号：US07873105B2

    公开(公告)日：2011-01-18

    申请号：US11096988

    申请日：2005-04-01

    Applicant: Bhaskar Sherigar ,  Anand Tongle

    Inventor： Bhaskar Sherigar ,  Anand Tongle

    IPC: H04B1/66

    CPC classification number: H04N19/42 ,  H04N19/12 ,  H04N19/126 ,  H04N19/159 ,  H04N19/186 ,  H04N19/44 ,  H04N19/61 ,  H04N19/70

    Abstract: Presented herein are optimized single inverse quantization engines for a plurality of standards. In one embodiment, there is presented a system for inverse quantizing quantized frequency coefficients. The system comprises an inverse quantizer for inverse quantizing video data encoded in accordance with a first encoding standard and for inverse quantizing video data encoded in accordance with a second encoding standard. In another embodiment, there is presented a decoder for decoding video data. The decoder comprises an inverse quantizer operable to inverse quantize video data encoded in accordance with a first encoding standard and for inverse quantizing video data encoded in accordance with a second encoding standard.

    Abstract translation: 这里呈现的是用于多个标准的优化的单反量子化引擎。 在一个实施例中，提出了用于对量化的频率系数进行逆量化的系统。 该系统包括逆量化器，用于对根据第一编码标准编码的视频数据进行逆量化，并且用于对根据第二编码标准编码的视频数据进行逆量化。 在另一实施例中，提供了一种用于对视频数据进行解码的解码器。 解码器包括逆量化器，其可操作以对根据第一编码标准编码的视频数据进行逆量化，并用于对根据第二编码标准编码的视频数据进行逆量化。

    Unified decoder architecture
    17.
    发明授权
    Unified decoder architecture 有权
    统一的解码器架构

    公开(公告)号：US07720294B2

    公开(公告)日：2010-05-18

    申请号：US10775652

    申请日：2004-02-09

    Applicant: Ravindra Bidnur ,  Ramadas Lakshmikanth Pai ,  Bhaskar Sherigar ,  Aniruddha Sane ,  Sandeep Bhatia ,  Gaurava Agarwal

    Inventor： Ravindra Bidnur ,  Ramadas Lakshmikanth Pai ,  Bhaskar Sherigar ,  Aniruddha Sane ,  Sandeep Bhatia ,  Gaurava Agarwal

    IPC: G06K9/36 ,  H04N7/12 ,  H04N11/02

    CPC classification number: H04N19/44 ,  H04N19/61 ,  H04N19/70

    Abstract: Presented herein is a unified decoder architecture. A system comprises a video decoder, instruction memory, and a host processor. The video decoder decodes the video data encoded with the particular standard. The instruction memory stores a first set of instructions and a second set of instructions. The first set of instructions are for decoding encoded video data according to a first encoding standard. The second set of instruction are for decoding encoded video data according to a second encoding standard. The host processor provides an indication to the video decoder indicating the particular encoding standard. The video decoder executes the first set of instructions if the indication indicates that the particular encoding standard is the first encoding standard and executes the second set of instructions if the indication indicates that the particular encoding standard is the second encoding standard.

    Abstract translation: 这里呈现的是统一的解码器架构。 系统包括视频解码器，指令存储器和主机处理器。 视频解码器解码用特定标准编码的视频数据。 指令存储器存储第一组指令和第二组指令。 第一组指令用于根据第一编码标准对编码的视频数据进行解码。 第二组指令用于根据第二编码标准对编码的视频数据进行解码。 主机处理器向视频解码器提供指示特定编码标准的指示。 如果指示指示特定编码标准是第一编码标准，则视频解码器执行第一组指令，并且如果指示指示特定编码标准是第二编码标准，则执行第二组指令。

    Hardware implementation of programmable controls for inverse quantizing with a plurality of standards
    19.
    发明申请
    Hardware implementation of programmable controls for inverse quantizing with a plurality of standards 审中-公开
    用于使用多个标准进行逆量化的可编程控制器的硬件实现

    公开(公告)号：US20070147496A1

    公开(公告)日：2007-06-28

    申请号：US11317578

    申请日：2005-12-23

    Applicant: Bhaskar Sherigar ,  Anand Tongle

    Inventor： Bhaskar Sherigar ,  Anand Tongle

    IPC: H04N11/04 ,  H04N7/12

    CPC classification number: H04N19/40 ,  H04N19/12 ,  H04N19/124 ,  H04N19/44

    Abstract: Presented herein are system(s), and method(s) for inverse quantizing data from a plurality of standards. In one embodiment, there is presented a system for decoding data. The system comprises a host processor and an inverse quantizer. The host processor provides inverse quantization parameters from a first standard and from a second standard that are transcoded to a particular format. The inverse quantizer receives the transcoded quantization parameters in the particular format and inverse quantizes quantized data quantized in accordance with the first standard and the second standard based on the transcoded quantization parameters.

    Abstract translation: 这里呈现的是用于从多个标准中逆量化数据的系统和方法。 在一个实施例中，提出了一种用于解码数据的系统。 该系统包括主处理器和逆量化器。 主机处理器提供来自第一标准和转码为特定格式的第二标准的反量化参数。 逆量化器接收特定格式的经转码的量化参数，并且基于代码转换的量化参数对根据第一标准和第二标准量化的量化数据进行逆量化。

    System, method, and apparatus for DC coefficient transformation
    20.
    发明申请
    System, method, and apparatus for DC coefficient transformation 审中-公开
    用于直流系数变换的系统，方法和装置

    公开(公告)号：US20060227874A1

    公开(公告)日：2006-10-12

    申请号：US11092256

    申请日：2005-03-29

    Applicant: Anand Tongle ,  Bhaskar Sherigar

    Inventor： Anand Tongle ,  Bhaskar Sherigar

    IPC: H04N11/04 ,  G06F17/14 ,  H04N7/12 ,  H04B1/66 ,  H04N11/02

    CPC classification number: G06F17/145 ,  H04N19/42 ,  H04N19/61

    Abstract: Presented herein are systems, methods, and apparatus for DC coefficient transformations. In one embodiment, there is presented a circuit for transforming a data matrix. The circuit comprises a controller and a plurality of stages. The controller fetches a row or column of elements from the data matrix. The plurality stages are associated with a plurality of elements in a product matrix and add or subtract each element of the row or column of elements to a plurality of running totals, wherein each of the plurality of elements in the product matrix are a function of the element.

    Abstract translation: 这里提出的是用于DC系数变换的系统，方法和装置。 在一个实施例中，提出了一种用于变换数据矩阵的电路。 电路包括控制器和多个级。 控制器从数据矩阵中获取一行或多列元素。 多个阶段与产品矩阵中的多个元素相关联，并且将元素的行或列的每个元素加或减为多个运行总计，其中乘积矩阵中的多个元素中的每一个都是 元件。

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