Abstract:
An apparatus for recovering high speed NRZ (non-return to zero) data is disclosed. A phase-locked loop (PLL) frequency-divides the frequency which is outputted from a voltage-controlled ring oscillator, and therefore, the physical limit of the PLL is not affected. The voltage-controlled ring oscillators are installed separately from the PLL, and the voltage-controlled ring oscillators are synchronized with the PLL in the frequency only. Further, the oscillators are phase-locked to the incoming NRZ data, and two voltage-controlled ring oscillators are enabled/disabled by the binary values of the NRZ data. Therefore, a bit synchronization is realized, and thus, the voltage-controlled ring oscillators are directly controlled by the NRZ data. Consequently, the NRZ data can be recovered up to the frequency band at which the voltage-controlled ring oscillators and a D flip flop operate.
Abstract:
Disclosed are a phase locked loop (PLL) of a digital scheme and a method thereof. More specifically, disclosed are a digital phase locked loop having a time-to-digital converter (TDC), a digital loop filter (DLF), and a digitally controlled oscillator (DCO), and that is designed to have a constant jitter characteristic at all times even though an operating condition of a circuit varies according to a process, voltage, temperature (PVT) change, and a method thereof.
Abstract:
Provided are a method and apparatus for dynamically managing hierarchical flows that more efficiently process packet traffic while maintaining compatibility with an existing packet data network in transferring both circuit traffic and packet traffic in a packet switched network. The method for dynamically managing hierarchical flows includes: receiving data packets, classifying the data packets according to attributes of the received data packets, and producing first flows; determining whether traffic of each of the first flows exceeds a predetermined bandwidth limit, and performing a packet drop process or producing second flows for first flows that exceed the bandwidth limit, according to a flow-specific policy; and performing second flow processing on the second flows according to a second flow policy. Only flows exceeding the bandwidth limit or causing congestion are hierarchically divided for management. This makes it possible to finely manage the flows without complex operations.
Abstract:
A system and method for time synchronization on a network is provided. According to the system and method for time synchronization, a slave clock device does not continuously receive a time synchronization message periodically transferred from a master clock device and thus does not correct its time upon all such occasions. Rather, the slave clock device requests time information from the master clock device only when the slave clock device needs to correct its time, and receives a time synchronization message transferred from the master clock device and compensates for its time deviation only while the slave clock device is activated, thereby reducing its power consumption and amount of computation.
Abstract:
Provided are a method and apparatus for dynamically managing hierarchical flows that more efficiently process packet traffic while maintaining compatibility with an existing packet data network in transferring both circuit traffic and packet traffic in a packet switched network. The method for dynamically managing hierarchical flows includes: receiving data packets, classifying the data packets according to attributes of the received data packets, and producing first flows; determining whether traffic of each of the first flows exceeds a predetermined bandwidth limit, and performing a packet drop process or producing second flows for first flows that exceed the bandwidth limit, according to a flow-specific policy; and performing second flow processing on the second flows according to a second flow policy. Only flows exceeding the bandwidth limit or causing congestion are hierarchically divided for management. This makes it possible to finely manage the flows without complex operations.
Abstract:
Provided are a data transceiver and method for performing equalization and pre-emphasis adaptive to the transmission characteristic of a transmitting part. The transceiver measures the signal attenuation characteristic of a transmission line of a receiving part using an input data signal input via the transmission line of the receiving part, decodes the distorted waveform of the input data signal, distorts the waveform of an output data signal beforehand using the measured signal attenuation characteristic of the transmission line of the receiving part, and transmits the output data signal via a transmission line of a transmitting part. Thus, when the output data signal is transmitted via the transmission line of the transmitting part, the waveform of the signal remains optimized.
Abstract:
An nB2P coding/decoding device having a line code function facilitating data transmission and data recovery in the transmission line or link, and a function of a channel code for detecting errors in the recovered data, is provided, including: an nB2P coding device for dividing n bit width parallel data into two data units each having a predetermined bit width, and serial-transmitting the resulting n+2 bit coded data to which two odd parity bits are added, with predetermined n+2 bit with block synchronization data which is orthogonal to the coded data; and an nB2P decoding device for detecting the block synchronization data from the serially transmitted data, converts serial data to parallel form of n+2 bits, checking for errors in the coded data using the odd parity, and removing the odd parity to decode them into the original n bit width parallel data.
Abstract:
A parallel processing-based time synchronization apparatus employs a double-filter structure based on parallel processing, providing more precise and reliable time synchronization between a master device and a slave device. A first filter is implemented as hardware so as to realize time synchronization despite cyclic synchronization message transmission at short intervals and the second filter is implemented as software so as to realize precise time synchronization.
Abstract:
A multi-layer data processing apparatus and method are provided. The multi-layer data processing apparatus includes a lower hierarchy processing unit configured to generate at least one lower hierarchy flow from input data using lower hierarchy information, and to allocate the generated lower hierarchy flows to a plurality of lower hierarchy processors to perform lower hierarchy processing in respect of the lower hierarchy flows in parallel; and a higher hierarchy processing unit configured to generate at least one higher hierarchy flow from data transmitted from the lower hierarchy processing unit using higher hierarchy information, and to allocate the generated higher hierarchy flows to a plurality of higher hierarchy processors to perform higher hierarchy processing in parallel in respect of the higher hierarchy flows.
Abstract:
Provided is an apparatus for changing Media Access Control (MAC) address, which is a conventional subscriber hardware identification address for identifying each subscriber, and a method thereof. The MAC address changing apparatus includes a frame receiving block for determining whether to change a source MAC address; a switch controlling block for controlling a switch; a change MAC address generating block for changing the source MAC address of the received frame; a change MAC address storing block for storing information of the change MAC address and the source MAC address corresponding thereto; a MAC address forwarding and lookup block for extracting output port information; a MAC address replacing block for forming an output frame by replacing the source MAC address; a MAC address storing block for storing a MAC address; and a frame transmitting block for transmitting the output frame.