公开(公告)号：US20080001211A1

公开(公告)日：2008-01-03

申请号：US11759044

申请日：2007-06-06

Applicant: Byung-Kyu Cho ,  Tae-Yong Kim ,  Choong-Ho Lee

Inventor： Byung-Kyu Cho ,  Tae-Yong Kim ,  Choong-Ho Lee

IPC: H01L21/336 ,  H01L29/76

CPC classification number: H01L27/11568 ,  B82Y10/00 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11531

Abstract: A NOR flash memory device includes a substrate having trenches that extend in a first direction and stepped portions that are arranged between the trenches. A bit region having a linear shape extends in a second direction substantially perpendicular to the first direction in the substrate. The bit region is doped with impurities. A first dielectric layer is on the substrate having the trenches. An electric charge trap layer is on the first dielectric layer. A second dielectric layer is on the electric charge trap layer. An upper electrode is on sidewalls of the trenches. The upper electrode has a spacer shape. Related fabrication methods are also described.

Abstract translation: NOR闪存器件包括具有沿第一方向延伸的沟槽的衬底和布置在沟槽之间的台阶部分。 具有直线形状的位区域沿着基板中基本上垂直于第一方向的第二方向延伸。 该位区掺杂有杂质。 第一电介质层位于具有沟槽的衬底上。 电荷陷阱层位于第一电介质层上。 第二介电层位于电荷陷阱层上。 上电极位于沟槽的侧壁上。 上电极具有间隔件形状。 还描述了相关的制造方法。

公开(公告)号：US20120132982A1

公开(公告)日：2012-05-31

申请号：US13282575

申请日：2011-10-27

Applicant: Chang-Hyun LEE ,  Byung-Kyu CHO ,  Jang-Hyun YOU ,  Albert FAYRUSHIN

Inventor： Chang-Hyun LEE ,  Byung-Kyu CHO ,  Jang-Hyun YOU ,  Albert FAYRUSHIN

IPC: H01L29/788

CPC classification number: H01L29/42364 ,  H01L21/02109 ,  H01L21/02304 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825

Abstract: A non-volatile memory device includes gate structures, an insulation layer pattern, and an isolation structure. Multiple gate structures being spaced apart from each other in a first direction are formed on a substrate. Ones of the gate structures extend in a second direction that is substantially perpendicular to the first direction. The substrate includes active regions and field regions alternately and repeatedly formed in the second direction. The insulation layer pattern is formed between the gate structures and has a second air gap therein. Each of the isolation structures extending in the first direction and having a first air gap between the gate structures, the insulation layer pattern, and the isolation structure is formed on the substrate in each field region.

Abstract translation: 非易失性存储器件包括栅极结构，绝缘层图案和隔离结构。 在第一方向上彼此间隔开的多个栅极结构形成在基板上。 栅极结构的一部分在基本上垂直于第一方向的第二方向上延伸。 衬底包括在第二方向上交替且重复地形成的有源区和场区。 绝缘层图案形成在栅极结构之间并且其中具有第二气隙。 在每个场区域的基板上形成有在第一方向上延伸并且在栅极结构之间具有第一空气间隙，绝缘层图案和隔离结构的隔离结构。

公开(公告)号：US20090221138A1

公开(公告)日：2009-09-03

申请号：US12379190

申请日：2009-02-13

Applicant: Hee-Soo KANG ,  Byung-Kyu CHO ,  Choong-Ho LEE ,  Dong-Uk CHOI

Inventor： Hee-Soo KANG ,  Byung-Kyu CHO ,  Choong-Ho LEE ,  Dong-Uk CHOI

IPC: H01L21/336

CPC classification number: H01L21/28052 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66545

Abstract: A method of manufacturing a semiconductor device, including forming a plurality of gate structures on a substrate, the gate structures each including a hard mask pattern stacked on a gate conductive pattern, forming an insulating layer pattern between the gate structures at least partially exposing a top surface of the hard mask pattern, forming a trench that exposes at least a top surface of the gate conductive pattern by selectively removing the hard mask pattern, and forming a silicide layer on the exposed gate conductive pattern.

Abstract translation: 一种制造半导体器件的方法，包括在衬底上形成多个栅极结构，所述栅极结构各自包括堆叠在栅极导电图案上的硬掩模图案，在栅极结构之间形成至少部分地暴露顶部的绝缘层图案 形成通过选择性地去除硬掩模图案而暴露出栅极导电图案的至少顶表面的沟槽，以及在暴露的栅极导电图案上形成硅化物层的沟槽。

公开(公告)号：US20110233636A1

公开(公告)日：2011-09-29

申请号：US13050320

申请日：2011-03-17

Applicant: Byung-kyu Cho ,  Kwang-soo Seol ,  Sung-hoi Hur ,  Jung-dal Choi

Inventor： Byung-kyu Cho ,  Kwang-soo Seol ,  Sung-hoi Hur ,  Jung-dal Choi

IPC: H01L29/78

CPC classification number: H01L21/26586 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

Abstract: A non-volatile memory device and a method of manufacturing the non-volatile memory device are disclosed. The non-volatile memory device includes a substrate, at least two gate structures on the substrate, and at least one impurity region in portions of the substrate between the at least two gate structures. The center of the at least one impurity region is horizontally offset from the center of a region between the at least two gate structures.

Abstract translation: 公开了非易失性存储器件和制造非易失性存储器件的方法。 非易失性存储器件包括衬底，衬底上的至少两个栅极结构，以及在至少两个栅极结构之间的衬底的部分中的至少一个杂质区域。 至少一个杂质区域的中心与至少两个栅极结构之间的区域的中心水平偏移。

公开(公告)号：US20080237685A1

公开(公告)日：2008-10-02

申请号：US11822548

申请日：2007-07-06

Applicant: Byung-Kyu Cho ,  Se-Hoon Lee ,  Kyu-Charn Park ,  Choong-Ho Lee

Inventor： Byung-Kyu Cho ,  Se-Hoon Lee ,  Kyu-Charn Park ,  Choong-Ho Lee

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

Abstract: In one embodiment, the semiconductor memory device includes a semiconductor substrate having projecting portions, a tunnel insulation layer formed over at least one of the projecting semiconductor substrate portions, and a floating gate structure disposed over the tunnel insulation layer. An upper portion of the floating gate structure is wider than a lower portion of the floating gate structure, and the lower portion of the floating gate structure has a width less than a width of the tunnel insulating layer. First insulation layer portions are formed in the semiconductor substrate and project from the semiconductor substrate such that the floating gate structure is disposed between the projecting first insulation layer portions. A dielectric layer is formed over the first insulation layer portions and the floating gate structure, and a control gate is formed over the dielectric layer.

Abstract translation: 在一个实施例中，半导体存储器件包括具有突出部分的半导体衬底，在至少一个突出半导体衬底部分上形成的隧道绝缘层，以及设置在隧道绝缘层上的浮动栅极结构。 浮动栅极结构的上部比浮动栅极结构的下部宽，并且浮动栅极结构的下部具有小于隧道绝缘层的宽度的宽度。 第一绝缘层部分形成在半导体衬底中并从半导体衬底突出，使得浮栅结构设置在突出的第一绝缘层部分之间。 在第一绝缘层部分和浮动栅极结构之上形成电介质层，并且在电介质层上形成控制栅极。