公开(公告)号：US20060030305A1

公开(公告)日：2006-02-09

申请号：US11201229

申请日：2005-08-09

Applicant: Chang-Jae Lee ,  Ki-Seon Ryu ,  Beum-Joon Kim

Inventor： Chang-Jae Lee ,  Ki-Seon Ryu ,  Beum-Joon Kim

IPC: H04M3/00

CPC classification number: H04W52/0235 ,  Y02D70/00

Abstract: A method of performing a ranging process between a base station and a mobile station in sleep mode in a wireless access system, wherein the base station provides the mobile station with an initial notification of a periodic ranging time that occurs during a sleep time interval and during which the mobile station is to perform the ranging process, the initial notification included in a first message indicating whether the mobile station should terminate sleep mode to receive downlink data, and wherein the base station provides the mobile station with subsequent notifications of periodic ranging times that occur during the sleep time interval, the subsequent notifications indicated in a second message, the second message transmitted to the mobile station as part of the ranging process such that the mobile station performs a plurality of ranging processes within the sleep time interval.

Abstract translation: 一种在无线接入系统中以休眠模式在基站与移动台之间进行测距处理的方法，其中所述基站向所述移动台提供在睡眠时间间隔期间和在休眠期间期间发生的周期性测距时间的初始通知 移动台将要执行测距过程的初始通知包括在指示移动台是否应当终止睡眠模式以接收下行链路数据的第一消息中，并且其中基站向移动台提供周期性测距时间的后续通知， 在睡眠时间间隔期间发生第二消息中指示的后续通知，将第二消息作为测距过程的一部分发送到移动台，使得移动台在睡眠时间间隔内执行多个测距过程。

公开(公告)号：US06353254B1

公开(公告)日：2002-03-05

申请号：US09717304

申请日：2000-11-22

Applicant: Chang-Jae Lee ,  Jae-Il Ju

Inventor： Chang-Jae Lee ,  Jae-Il Ju

IPC: H01L2900

CPC classification number: H01L21/3081 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76283

Abstract: The present invention relates to a device isolation structure and a device isolation method in a semiconductor power IC. The device isolation structure according to the present invention includes: a semiconductor substrate including a high voltage region and a low voltage region; a trench overlapping the high voltage device region of the semiconductor substrate and an interfacing region formed between the high voltage device region and the low voltage device region; a fourth insulating film, a fifth insulating film, and a conductive film sequentially layered in the trench; a first insulating film pattern formed on the semiconductor substrate including the trench; and field insulating films respectively formed on the trench and on a portion of an upper surface of the semiconductor substrate which is exposed out of the first insulating film pattern. The present invention has several advantages concerning manufacturing costs and reliability, some of which being achieved by forming a thermal oxide film in an empty space of the conductive film by which oxygen is permeated thereinto and thus restraining breakdown from being generated between high voltage devices at a high voltage.

Abstract translation: 本发明涉及半导体功率IC中的器件隔离结构和器件隔离方法。 根据本发明的器件隔离结构包括：包括高电压区域和低电压区域的半导体衬底; 与半导体衬底的高压器件区域重叠的沟槽和形成在高电压器件区域和低电压器件区域之间的界面区域; 第四绝缘膜，第五绝缘膜和顺序层叠在沟槽中的导电膜; 形成在包括沟槽的半导体衬底上的第一绝缘膜图案; 以及分别形成在所述沟槽上和所述半导体衬底的从所述第一绝缘膜图案露出的所述上表面的一部分上的场绝缘膜。 本发明具有制造成本和可靠性方面的几个优点，其中一些优点是通过在导电膜的空的空间中形成热氧化膜来实现的，氧空气通过氧化膜渗入其中，从而抑制在高压装置之间产生的击穿 高压。

公开(公告)号：US06303493B1

公开(公告)日：2001-10-16

申请号：US08924534

申请日：1997-09-05

Applicant: Chang Jae Lee

Inventor： Chang Jae Lee

IPC: H01L2144

CPC classification number: H01L29/41783 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Wiring for a semiconductor device which is suitable for high density device packing, and a method for forming the same, are disclosed. The wiring includes: impurity regions formed in a substrate on both sides of an insulated gate electrode; a first conduction layer formed on the impurity regions; and a second conduction layer formed in contact with the first conduction layer on one side of the gate electrode. The method includes the steps of: forming impurity regions in a substrate on both sides of an insulated gate electrode; forming a first conduction layer on the impurity regions; and forming a second conduction layer in contact on one side of the gate electrode with the first conduction layer.

公开(公告)号：US5897350A

公开(公告)日：1999-04-27

申请号：US780173

申请日：1996-12-24

Applicant: Chang-Jae Lee ,  Won-Suck Yang

Inventor： Chang-Jae Lee ,  Won-Suck Yang

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/10852

Abstract: A memory cell structure for a semiconductor memory device and fabricating method thereof, which is suitable for DRAM memory devices of 256M or more capacity requiring a very high degree of integration, which comprises the steps of forming sequentially first and second random layers on a semiconductor substrate; patterning a first photoresist layer having a limited line width on the second random layer; patterning the second random layer using as a mask the patterned first photoresist layer; removing the first photoresist layer, and then patterning the second photoresist layer having the limited line width between the pattern of the second random layer; patterning the first random layer using as a mask the second photoresist layer which is so patterned so as to be placed between the pattern of the second random layer; and removing the second random layer and the second photoresist layer.

Abstract translation: 一种用于半导体存储器件的存储单元结构及其制造方法，其适用于需要非常高集成度的256M或更大容量的DRAM存储器件，其包括以下步骤：在半导体衬底上形成顺序的第一和第二随机层 ; 在第二随机层上图案化具有有限线宽度的第一光致抗蚀剂层; 使用图案化的第一光致抗蚀剂层作为掩模来图案化第二随机层; 去除第一光致抗蚀剂层，然后在第二无规层的图案之间图案化具有有限线宽度的第二光致抗蚀剂层; 使用如此构图的第二光致抗蚀剂层作为掩模来构图第一随机层，以便放置在第二随机层的图案之间; 以及去除所述第二无规层和所述第二光致抗蚀剂层。

公开(公告)号：US5866458A

公开(公告)日：1999-02-02

申请号：US520440

申请日：1995-08-29

Applicant: Chang Jae Lee

Inventor： Chang Jae Lee

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/82

CPC classification number: H01L21/823878

Abstract: A CMOS fabrication method includes the steps of providing a substrate having a surface, forming a first conductive well adjacent to the surface of the substrate, forming a second conductive well adjacent to the surface of the substrate, a portion of the first conductive well overlapping a portion of the second conductive well, forming a field oxide in the overlapping portion of the first and second conductive wells forming a first gate over the first conductive well and a second gate over the second conductive well, masking the first conductive well and implanting second conductive impurities on the second conductive well and masking the second conductive well and implanting first conductive impurities on the first conductive well.

Abstract translation: CMOS制造方法包括以下步骤：提供具有表面的衬底，形成与衬底表面相邻的第一导电阱，形成与衬底表面相邻的第二导电阱，第一导电阱的一部分与 部分第二导电阱，在第一和第二导电阱的重叠部分中形成场氧化物，在第一导电阱上形成第一栅极，在第二导电阱上形成第二栅极，掩蔽第一导电阱并注入第二导电阱 在第二导电阱上的杂质并掩蔽第二导电阱并且在第一导电阱上注入第一导电杂质。

公开(公告)号：US5801086A

公开(公告)日：1998-09-01

申请号：US893739

申请日：1997-07-11

Applicant: Chang Jae Lee

Inventor： Chang Jae Lee

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/44 ,  H01L21/60 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/28518

Abstract: A method for forming a contact between a conductive layer and a portion of the substrate during manufacture of a semiconductor device is disclosed. The process includes the steps of: (a) covering a semiconductor substrate with an insulating layer, and forming a contact hole on the portion where a contact is to be formed; (b) forming a metal layer on the whole surface of the substrate, and implanting positive ions into the metal layer; and (c) heat-treating the whole substrate so as to form a silicide layer. The metals used are those which can react with silicon to form a silicide, and may be selected from high melting point metals including Co, Ti, Ta, Ni, Mo, and Hf. The ions used are ions including H+ or halogen element ions, and a heat treatment is carried out so that the implanted positive ions may spread on/in the grain boundaries, or that the positive ions may bond with dangling bonds. Further, a silicidation heat treatment is carried out so that the silicide would be formed on the portion where the metal and the silicon substrate contact together. These heat treatments may be carried out simultaneously. The heat treatment for the spreading of the positive ions is carried out at a low temperature of about 300.degree.-500.degree. C., while the heat treatment of the silicidation reaction is carried out at a proper temperature depending on the metal used.

Abstract translation: 公开了一种用于在制造半导体器件期间在导电层和衬底的一部分之间形成接触的方法。 该方法包括以下步骤：（a）用绝缘层覆盖半导体衬底，并在要形成接触的部分上形成接触孔; （b）在基板的整个表面上形成金属层，并将正离子注入到金属层中; 和（c）对整个基板进行热处理以形成硅化物层。 使用的金属是可以与硅反应形成硅化物的金属，并且可以选自包括Co，Ti，Ta，Ni，Mo和Hf的高熔点金属。 使用的离子包括H +或卤素元素离子，并且进行热处理，使得注入的正离子可以在晶界上/在晶界上扩散，或者正离子可以与悬挂键结合。 此外，进行硅化热处理，使得硅化物将形成在金属和硅衬底接触在一起的部分上。 这些热处理可以同时进行。 用于扩散正离子的热处理在约300-500℃的低温下进行，而硅化反应的热处理根据所使用的金属在适当的温度下进行。

公开(公告)号：US5741722A

公开(公告)日：1998-04-21

申请号：US698520

申请日：1996-08-15

Applicant: Chang Jae Lee

Inventor： Chang Jae Lee

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L28/40

Abstract: A semiconductor device capacitor structure comprises a semiconductor substrate having an impurity diffusion region; an insulating layer formed on the semiconductor substrate and having a contact hole on the impurity diffusion region; a first lower electrode of a half ring type formed on the insulating film along an upper edge of the contact hole; a second lower electrode formed on a surface of the substrate exposed through the contact hole, a wall of the contact hole, and the first lower electrode; a dielectric layer formed on the first and second lower electrodes; and an upper electrode formed on the dielectric layer. This structure increases capacitance, thereby improving the characteristics and reliability of the device.

Abstract translation: 半导体器件电容器结构包括具有杂质扩散区域的半导体衬底; 绝缘层，其形成在所述半导体衬底上并且在所述杂质扩散区上具有接触孔; 沿所述接触孔的上边缘形成在所述绝缘膜上的半环型的第一下电极; 形成在通过接触孔露出的基板的表面上的第二下电极，接触孔的壁和第一下电极; 形成在第一和第二下部电极上的电介质层; 以及形成在电介质层上的上电极。 该结构增加了电容，从而提高了器件的特性和可靠性。

公开(公告)号：US5604138A

公开(公告)日：1997-02-18

申请号：US357961

申请日：1994-12-15

Applicant: Chang-Jae Lee ,  Young-Jin Song

Inventor： Chang-Jae Lee ,  Young-Jin Song

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/469 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/6659 ,  H01L21/28123

Abstract: A process for forming an MOS semiconductor device having an LDD structure is disclosed, which may include the steps of: forming a first insulating layer on a semiconductor substrate; forming a conductive layer on the first insulating layer; forming a second insulating layer on the conductive layer; forming a third insulating layer on the second insulating layer; forming an etch inhibiting layer pattern for forming an over-sized gate on a relevant area of the second insulating layer; removing the second and third insulating layers and the conductive layer excluding the portions protected from the etch inhibiting layer, so as to form a stacked pattern consisting of the residual second insulating layer/the third insulating layer/the conductive layer; forming a first impurity ion buried layer on a relevant portion of the semiconductor substrate utilizing the stacked pattern for formation of a source/drain region; removing the etch inhibiting layer; removing an edge portion of the remaining second insulating layer of the stacked pattern for forming the final gate; removing the residual third insulating layer of the stacked pattern; etching the residual conductive layer by using the partly removed second insulating layer as the mask to form the final gate; forming a second impurity ion buried layer on the relevant portion of the semiconductor substrate for forming the LDD structure; forming a fourth insulating layer on the whole surface of the wafer; and activating the first and second ion buried layers.

Abstract translation: 公开了一种用于形成具有LDD结构的MOS半导体器件的工艺，其可以包括以下步骤：在半导体衬底上形成第一绝缘层; 在所述第一绝缘层上形成导电层; 在所述导电层上形成第二绝缘层; 在所述第二绝缘层上形成第三绝缘层; 形成用于在所述第二绝缘层的相关区域上形成超大尺寸栅极的蚀刻抑制层图案; 除去不受蚀刻抑制层保护的部分的第二绝缘层和第三绝缘层和导电层，以形成由残留的第二绝缘层/第三绝缘层/导电层组成的层叠图案; 使用用于形成源极/漏极区域的堆叠图案在半导体衬底的相关部分上形成第一杂质离子掩埋层; 去除蚀刻抑制层; 去除用于形成最终栅极的层叠图案的剩余第二绝缘层的边缘部分; 去除堆叠图案的残余第三绝缘层; 通过使用部分去除的第二绝缘层作为掩模来蚀刻残留导电层以形成最终栅极; 在所述半导体衬底的相关部分上形成第二杂质离子掩埋层以形成所述LDD结构; 在晶片的整个表面上形成第四绝缘层; 并激活第一和第二离子掩埋层。

公开(公告)号：US5583064A

公开(公告)日：1996-12-10

申请号：US376517

申请日：1995-01-23

Applicant: Chang-Jae Lee ,  Hyuk-Jin Kwon

Inventor： Chang-Jae Lee ,  Hyuk-Jin Kwon

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/265 ,  H01L21/302 ,  H01L21/304 ,  H01L21/76

CPC classification number: H01L29/66613

Abstract: A recess is formed (dug) into the surface of a substrate to form a gate channel in the recess, so that a monocrystalline source/drain region can be formed at a level higher than that of the channel. The process includes the steps of: (a) forming an insulating layer and an oxidation preventing layer on a semiconductor substrate, and removing the oxidation preventing layer of a channel region of the transistor by an etching process; (b) forming an oxide layer on the channel region of the transistor by thermally oxidizing the semiconductor substrate, removing the oxidation preventing layer, and carrying out a first ion implantation on the whole surface; (c) removing the oxide layer, and forming the channel of the transistor in the form of a recess so as for the recess to be positioned lower than the surface of the substrate; (d) forming a gate electrode in the recess; and (e) carrying out a second ion implantation on the whole surface, and carrying out a heat treatment to form a source/drain region.

Abstract translation: 在衬底的表面中形成（挖出）凹部以在凹部中形成栅极沟道，使得单晶源极/漏极区域可以形成在高于沟道的水平。 该方法包括以下步骤：（a）在半导体衬底上形成绝缘层和防氧化层，并通过蚀刻工艺除去晶体管的沟道区的氧化防止层; （b）通过热氧化半导体衬底，去除氧化防止层，并在整个表面上进行第一离子注入，在晶体管的沟道区上形成氧化物层; （c）去除所述氧化物层，以及形成所述晶体管的沟槽形式，以使所述凹部定位成低于所述衬底的表面; （d）在所述凹部中形成栅电极; 和（e）在整个表面上进行第二离子注入，进行热处理以形成源/漏区。

公开(公告)号：US5468665A

公开(公告)日：1995-11-21

申请号：US376514

申请日：1995-01-23

Applicant: Chang-Jae Lee ,  Hyunsang Hwang

Inventor： Chang-Jae Lee ,  Hyunsang Hwang

IPC: H01L21/336 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/335

CPC classification number: H01L29/6659 ,  H01L21/823864

Abstract: In the method of present invention, an LDD MOSFET is formed without using a side wall spacer as an ion implantation inhibiting layer. The process includes the steps of: forming a first insulating layer, a conductive layer and an auxiliary layer upon a semiconductor substrate, removing relevant portions of the auxiliary layer to form an auxiliary layer pattern such as a gate pattern on the conductive layer; depositing a temporary layer on the auxiliary layer pattern and on the exposed conductive layer, and etching it back to form a temporary layer spacer on the side wall of the auxiliary layer pattern; removing relevant portions of the conductive layer utilizing the auxiliary layer pattern and the temporary layer spacer as a mask, and forming a high concentration first dopant buried layer within the semiconductor substrate; and removing the temporary layer spacer, forming a gate electrode by etching the conductive layer utilizing the auxiliary layer pattern as a mask, and forming a low concentration second dopant buried layer within the semiconductor substrate. Applications to form CMOS devices are also disclosed.

Abstract translation: 在本发明的方法中，形成LDD MOSFET，而不使用侧壁间隔物作为离子注入抑制层。 该方法包括以下步骤：在半导体衬底上形成第一绝缘层，导电层和辅助层，去除辅助层的相关部分以在导电层上形成诸如栅极图案的辅助层图案; 在辅助层图案和暴露的导电层上沉积临时层，并将其蚀刻回辅助层图案的侧壁上形成临时层间隔物; 使用辅助层图案和临时层间隔物作为掩模去除导电层的相关部分，并在半导体衬底内形成高浓度第一掺杂剂掩埋层; 并且移除临时层间隔物，通过利用辅助层图案作为掩模蚀刻导电层形成栅电极，以及在半导体衬底内形成低浓度第二掺杂剂掩埋层。 还公开了用于形成CMOS器件的应用。