公开(公告)号：US5583064A

公开(公告)日：1996-12-10

申请号：US376517

申请日：1995-01-23

Applicant: Chang-Jae Lee ,  Hyuk-Jin Kwon

Inventor： Chang-Jae Lee ,  Hyuk-Jin Kwon

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/265 ,  H01L21/302 ,  H01L21/304 ,  H01L21/76

CPC classification number: H01L29/66613

Abstract: A recess is formed (dug) into the surface of a substrate to form a gate channel in the recess, so that a monocrystalline source/drain region can be formed at a level higher than that of the channel. The process includes the steps of: (a) forming an insulating layer and an oxidation preventing layer on a semiconductor substrate, and removing the oxidation preventing layer of a channel region of the transistor by an etching process; (b) forming an oxide layer on the channel region of the transistor by thermally oxidizing the semiconductor substrate, removing the oxidation preventing layer, and carrying out a first ion implantation on the whole surface; (c) removing the oxide layer, and forming the channel of the transistor in the form of a recess so as for the recess to be positioned lower than the surface of the substrate; (d) forming a gate electrode in the recess; and (e) carrying out a second ion implantation on the whole surface, and carrying out a heat treatment to form a source/drain region.

Abstract translation: 在衬底的表面中形成（挖出）凹部以在凹部中形成栅极沟道，使得单晶源极/漏极区域可以形成在高于沟道的水平。 该方法包括以下步骤：（a）在半导体衬底上形成绝缘层和防氧化层，并通过蚀刻工艺除去晶体管的沟道区的氧化防止层; （b）通过热氧化半导体衬底，去除氧化防止层，并在整个表面上进行第一离子注入，在晶体管的沟道区上形成氧化物层; （c）去除所述氧化物层，以及形成所述晶体管的沟槽形式，以使所述凹部定位成低于所述衬底的表面; （d）在所述凹部中形成栅电极; 和（e）在整个表面上进行第二离子注入，进行热处理以形成源/漏区。

公开(公告)号：US20110135811A1

公开(公告)日：2011-06-09

申请号：US12758442

申请日：2010-04-12

Applicant: Hyuk-Jin Kwon ,  Hyo-Seung Nam ,  Tae-Ho Kim ,  Jong-Sik Kim ,  Jung-Wook Seo

Inventor： Hyuk-Jin Kwon ,  Hyo-Seung Nam ,  Tae-Ho Kim ,  Jong-Sik Kim ,  Jung-Wook Seo

IPC: B05D5/12 ,  C09D5/00

CPC classification number: H05K3/244 ,  C23C18/1608 ,  C23C18/1651 ,  C23C18/1841 ,  C23C18/1844 ,  C23C18/2086 ,  H05K2203/073 ,  H05K2203/0789

Abstract: Disclosed is a solution for inhibiting palladium activity including an aqueous halogenic acid solution as a pre-treatment solution which may be used before an electroless plating of a printed circuit board to prevent bad plating and a method for preventing bad plating by using the same. More particularly, disclosed is a solution for inhibiting palladium activity including 0.1 to 10 mol of an aqueous halogenic acid solution as a pre-treatment solution which may be used before an ENIG plating or ENEPIG plating of a printed circuit board to prevent bad plating.Disclosed is also a method for preventing bad plating by minimizing defects of shorts between patterns which are caused by plating spreading during the surface treatment of a printed circuit board having fine patterns.

Abstract translation: 公开了一种用于抑制钯活性的溶液，包括作为预处理溶液的含水卤酸溶液，其可以在印刷电路板的无电镀以防止不良电镀之前使用，以及通过使用它们来防止不良电镀的方法。 更具体地，公开了一种用于抑制钯活性的溶液，包括0.1至10mol的卤酸水溶液作为预处理溶液，其可以在印刷电路板的ENIG电镀或ENEPIG电镀之前使用以防止不良电镀。 还公开了一种通过使在具有精细图案的印刷电路板的表面处理期间由电镀扩展引起的图案之间的短路的缺陷的最小化来防止不良镀覆的方法。

公开(公告)号：US07455076B2

公开(公告)日：2008-11-25

申请号：US11032103

申请日：2005-01-11

Applicant: Hyuk-Jin Kwon ,  Jong-Chul Park

Inventor： Hyuk-Jin Kwon ,  Jong-Chul Park

IPC: F16K3/18

CPC classification number: F16K3/34 ,  F16K1/222 ,  F16K1/223 ,  F16K3/0209 ,  F16K3/32 ,  F16K51/02 ,  Y10T137/7761 ,  Y10T137/8696 ,  Y10T137/87378

Abstract: An apparatus and method for controlling exhaust produced by a reactive chamber is provided. The apparatus for controlling exhaust may include, for example, a valve body having an exhaust hole for the exhaust to pass through, and may include a first and second valve which regulate the opening and/or the closing of the exhaust hole. A control device may control the operation of the first and second valves based on the internal pressure of the reactive chamber.

Abstract translation: 提供了一种用于控制由反应室产生的排气的装置和方法。 用于控制排气的装置可以包括例如具有用于排气通过的排气孔的阀体，并且可以包括调节排气孔的打开和/或关闭的第一和第二阀。 控制装置可以基于反应室的内部压力来控制第一和第二阀的操作。

公开(公告)号：US07326619B2

公开(公告)日：2008-02-05

申请号：US10902642

申请日：2004-07-28

Applicant: Jong-Chul Park ,  Jun Seo ,  Tae-Hyuk Ahn ,  Hyuk-Jin Kwon ,  Jong-Heui Song ,  Dae-Keun Kang

Inventor： Jong-Chul Park ,  Jun Seo ,  Tae-Hyuk Ahn ,  Hyuk-Jin Kwon ,  Jong-Heui Song ,  Dae-Keun Kang

IPC: H01L21/31 ,  H01L21/336

CPC classification number: H01L29/66553 ,  H01L29/66621 ,  H01L29/7834

Abstract: A method according to some embodiments of the invention includes defining an active region by forming a trench device isolation region on an integrated substrate, forming a mask pattern that exposes a channel sub-region of the active region and the trench device isolation region adjacent to the channel sub-region, etching the trench device isolation region, which is exposed by the mask pattern, to be recessed to a first depth using the mask pattern as an etch mask, etching the channel sub-region to form a gate trench having a second depth that is deeper than the first depth using the mask pattern as an etch mask, and forming a recess gate that fills the gate trench.

Abstract translation: 根据本发明的一些实施例的方法包括通过在集成衬底上形成沟槽器件隔离区域来限定有源区域，形成掩模图案，其暴露有源区域的沟道子区域和与该区域相邻的沟槽器件隔离区域 使用掩模图案作为蚀刻掩模蚀刻由掩模图案曝光的沟槽器件隔离区域，以凹陷到第一深度，蚀刻沟道子区域以形成栅极沟槽，栅极沟道具有第二 深度比使用掩模图案的第一深度深的蚀刻掩模，以及形成填充栅极沟槽的凹槽。

公开(公告)号：US08183070B2

公开(公告)日：2012-05-22

申请号：US12271775

申请日：2008-11-14

Applicant: Seok-Won Kim ,  Won-Joon Ho ,  Hyuk-Jin Kwon ,  Chang-Mo Yoo

Inventor： Seok-Won Kim ,  Won-Joon Ho ,  Hyuk-Jin Kwon ,  Chang-Mo Yoo

IPC: H01L33/00

CPC classification number: H01L27/124 ,  G02F1/1368 ,  G02F2001/136236 ,  G02F2201/40 ,  G03F7/40 ,  G03F7/427 ,  H01L27/1288

Abstract: A method of fabricating an array substrate for a liquid crystal display device includes: forming an initial photoresist (PR) pattern on a metallic material layer; etching the metallic material layer using the initial PR pattern as an etching mask to form the data line and a metallic material pattern, wherein the initial PR pattern is disposed on the data line; performing a first ashing process onto the initial PR pattern to partially remove the initial PR pattern so as to form a first ashed PR pattern, the first ashed PR pattern having a smaller width and a smaller thickness than the initial PR pattern such that end portions of the data line are exposed by the first ashed PR pattern; etching the intrinsic amorphous silicon layer and the impurity-doped amorphous silicon layer by a first dry-etching process; forming a source electrode and a drain electrode on the substrate.

Abstract translation: 制造液晶显示装置阵列基板的方法包括：在金属材料层上形成初始光致抗蚀剂（PR）图案; 使用初始PR图案蚀刻金属材料层作为蚀刻掩模以形成数据线和金属材料图案，其中初始PR图案设置在数据线上; 对初始PR图案执行第一灰化处理以部分地去除初始PR图案以形成第一灰化PR图案，第一灰化PR图案具有比初始PR图案更小的宽度和更小的厚度， 数据线由第一个灰色PR图案曝光; 通过第一干蚀刻工艺蚀刻本征非晶硅层和杂质掺杂非晶硅层; 在基板上形成源电极和漏电极。

公开(公告)号：US07531414B2

公开(公告)日：2009-05-12

申请号：US11956153

申请日：2007-12-13

Applicant: Jong-Chul Park ,  Jun Seo ,  Tae-Hyuk Ahn ,  Hyuk-Jin Kwon ,  Jong-Heui Song ,  Dae-Keun Kang

Inventor： Jong-Chul Park ,  Jun Seo ,  Tae-Hyuk Ahn ,  Hyuk-Jin Kwon ,  Jong-Heui Song ,  Dae-Keun Kang

IPC: H01L21/31 ,  H01L21/336

CPC classification number: H01L29/66553 ,  H01L29/66621 ,  H01L29/7834

Abstract: A method according to some embodiments of the invention includes defining an active region by forming a trench device isolation region on an integrated substrate, forming a mask pattern that exposes a channel sub-region of the active region and the trench device isolation region adjacent to the channel sub-region, etching the trench device isolation region, which is exposed by the mask pattern, to be recessed to a first depth using the mask pattern as an etch mask, etching the channel sub-region to form a gate trench having a second depth that is deeper than the first depth using the mask pattern as an etch mask, and forming a recess gate that fills the gate trench.

Abstract translation: 根据本发明的一些实施例的方法包括通过在集成衬底上形成沟槽器件隔离区域来限定有源区域，形成掩模图案，其暴露有源区域的沟道子区域和与该区域相邻的沟槽器件隔离区域 使用掩模图案作为蚀刻掩模蚀刻由掩模图案曝光的沟槽器件隔离区域，以凹陷到第一深度，蚀刻沟道子区域以形成栅极沟槽，栅极沟道具有第二 深度比使用掩模图案的第一深度深的蚀刻掩模，以及形成填充栅极沟槽的凹槽。

公开(公告)号：US20080090356A1

公开(公告)日：2008-04-17

申请号：US11956153

申请日：2007-12-13

Applicant: Jong-Chul PARK ,  Jun SEO ,  Tae-Hyuk AHN ,  Hyuk-Jin KWON ,  Jong-Heui SONG ,  Dae-Keun KANG

Inventor： Jong-Chul PARK ,  Jun SEO ,  Tae-Hyuk AHN ,  Hyuk-Jin KWON ,  Jong-Heui SONG ,  Dae-Keun KANG

IPC: H01L21/336

CPC classification number: H01L29/66553 ,  H01L29/66621 ,  H01L29/7834

Abstract: A method according to some embodiments of the invention includes defining an active region by forming a trench device isolation region on an integrated substrate, forming a mask pattern that exposes a channel sub-region of the active region and the trench device isolation region adjacent to the channel sub-region, etching the trench device isolation region, which is exposed by the mask pattern, to be recessed to a first depth using the mask pattern as an etch mask, etching the channel sub-region to form a gate trench having a second depth that is deeper than the first depth using the mask pattern as an etch mask, and forming a recess gate that fills the gate trench.

Abstract translation: 根据本发明的一些实施例的方法包括通过在集成衬底上形成沟槽器件隔离区域来限定有源区域，形成掩模图案，其暴露有源区域的沟道子区域和与该区域相邻的沟槽器件隔离区域 使用掩模图案作为蚀刻掩模蚀刻由掩模图案曝光的沟槽器件隔离区域，以凹陷到第一深度，蚀刻沟道子区域以形成栅极沟槽，栅极沟道具有第二 深度比使用掩模图案的第一深度深的蚀刻掩模，以及形成填充栅极沟槽的凹槽。

公开(公告)号：US20070210334A1

公开(公告)日：2007-09-13

申请号：US11698155

申请日：2007-01-26

Applicant: Young-Soo Lim ,  Yong-Sun Ko ,  Hyuk-Jin Kwon ,  Jae-Seung Hwang

Inventor： Young-Soo Lim ,  Yong-Sun Ko ,  Hyuk-Jin Kwon ,  Jae-Seung Hwang

IPC: H01L31/00

CPC classification number: H01L45/143 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: Example embodiments relate to a semiconductor memory device and a method of fabricating the same. Other example embodiments relate to a phase change memory device and a method of fabricating the same. There are provided a phase change memory device and a method of fabricating the same for improving or maximizing a production yield. The method comprises: after first removing a first hard mask layer used to form a contact pad electrically connected to a semiconductor substrate, forming a lower electrode to be electrically connected to the contact pad through a first contact hole in a first interlayer insulating layer formed on the contact pad and to have a thickness equal or similar to a thickness of the first interlayer insulating layer; and forming a phase change layer and an upper electrode on the lower electrode. Because change of the resistance value of the lower electrode is reduced or prevented, which has been caused due to a non-uniform thickness of a conventional first hard mask layer, a production yield may be improved.

Abstract translation: 示例性实施例涉及半导体存储器件及其制造方法。 其他示例性实施例涉及相变存储器件及其制造方法。 提供了一种相变存储器件及其制造方法，用于改善或最大化产量。 该方法包括：在首先去除用于形成与半导体衬底电连接的接触焊盘的第一硬掩模层之后，通过形成在第一层间绝缘层上的第一层间绝缘层中的第一接触孔形成下电极以与接触焊盘电连接 所述接触焊盘的厚度等于或类似于所述第一层间绝缘层的厚度; 并在下电极上形成相变层和上电极。 由于由于常规的第一硬掩模层的厚度不均匀而导致的下部电极的电阻值的变化被降低或防止，所以可以提高生产率。

公开(公告)号：US20090294781A1

公开(公告)日：2009-12-03

申请号：US12271775

申请日：2008-11-14

Applicant: Seok-Won KIM ,  Won-Joon Ho ,  Hyuk-Jin Kwon ,  Chang-Mo Yoo

Inventor： Seok-Won KIM ,  Won-Joon Ho ,  Hyuk-Jin Kwon ,  Chang-Mo Yoo

IPC: H01L21/336 ,  H01L33/00

CPC classification number: H01L27/124 ,  G02F1/1368 ,  G02F2001/136236 ,  G02F2201/40 ,  G03F7/40 ,  G03F7/427 ,  H01L27/1288

Abstract: A method of fabricating an array substrate for a liquid crystal display device includes: forming an initial photoresist (PR) pattern on a metallic material layer; etching the metallic material layer using the initial PR pattern as an etching mask to form the data line and a metallic material pattern, wherein the initial PR pattern is disposed on the data line; performing a first ashing process onto the initial PR pattern to partially remove the initial PR pattern so as to form a first ashed PR pattern, the first ashed PR pattern having a smaller width and a smaller thickness than the initial PR pattern such that end portions of the data line are exposed by the first ashed PR pattern; etching the intrinsic amorphous silicon layer and the impurity-doped amorphous silicon layer by a first dry-etching process; forming a source electrode and a drain electrode on the substrate.

Abstract translation: 制造液晶显示装置阵列基板的方法包括：在金属材料层上形成初始光致抗蚀剂（PR）图案; 使用初始PR图案蚀刻金属材料层作为蚀刻掩模以形成数据线和金属材料图案，其中初始PR图案设置在数据线上; 对初始PR图案执行第一灰化处理以部分地去除初始PR图案以形成第一灰化PR图案，第一灰化PR图案具有比初始PR图案更小的宽度和更小的厚度， 数据线由第一个灰色PR图案曝光; 通过第一干蚀刻工艺蚀刻本征非晶硅层和杂质掺杂非晶硅层; 在基板上形成源电极和漏电极。

公开(公告)号：US20050042833A1

公开(公告)日：2005-02-24

申请号：US10902642

申请日：2004-07-28

Applicant: Jong-Chul Park ,  Jun Seo ,  Tae-Hyuk Ahn ,  Hyuk-Jin Kwon ,  Jong-Heui Song ,  Dae-Keun Kang

Inventor： Jong-Chul Park ,  Jun Seo ,  Tae-Hyuk Ahn ,  Hyuk-Jin Kwon ,  Jong-Heui Song ,  Dae-Keun Kang

IPC: H01L21/336 ,  H01L21/4763 ,  H01L29/78

CPC classification number: H01L29/66553 ,  H01L29/66621 ,  H01L29/7834

Abstract: A method according to some embodiments of the invention includes defining an active region by forming a trench device isolation region on an integrated substrate, forming a mask pattern that exposes a channel sub-region of the active region and the trench device isolation region adjacent to the channel sub-region, etching the trench device isolation region, which is exposed by the mask pattern, to be recessed to a first depth using the mask pattern as an etch mask, etching the channel sub-region to form a gate trench having a second depth that is deeper than the first depth using the mask pattern as an etch mask, and forming a recess gate that fills the gate trench.

Abstract translation: 根据本发明的一些实施例的方法包括通过在集成衬底上形成沟槽器件隔离区域来限定有源区域，形成掩模图案，其暴露有源区域的沟道子区域和与该区域相邻的沟槽器件隔离区域 使用掩模图案作为蚀刻掩模蚀刻由掩模图案曝光的沟槽器件隔离区域，以凹陷到第一深度，蚀刻沟道子区域以形成栅极沟槽，栅极沟道具有第二 深度比使用掩模图案的第一深度深的蚀刻掩模，以及形成填充栅极沟槽的凹槽。