公开(公告)号：US20050272250A1

公开(公告)日：2005-12-08

申请号：US11147953

申请日：2005-06-07

Applicant: Cheol-Ju Yun ,  Tae-Young Chung ,  In-Ho Nam

Inventor： Cheol-Ju Yun ,  Tae-Young Chung ,  In-Ho Nam

IPC: H01L21/28 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/48 ,  H01L21/50 ,  H01L21/60 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108

CPC classification number: H01L27/10885 ,  H01L21/486 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5226 ,  H01L27/10814 ,  H01L27/10855 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In an embodiment a method of forming self-aligned contacts in a semiconductor memory device includes: forming conductive stacks of conductive layers on a semiconductor substrate; forming insulating spacer layers on sidewalls of the conductive stacks; forming an insulating layer; forming a capping insulating layer covering portions of the insulating layer; and forming conductive pads that fill the contact holes to contact the semiconductor substrate. The capping insulating layer has a function of a buffer, so an etched amount of mask layers insulating the conductive layers is minimized, and a probability of a short circuit between capacitor electrodes and the conductive stacks is greatly reduced.

Abstract translation: 在一个实施例中，在半导体存储器件中形成自对准触点的方法包括：在半导体衬底上形成导电层的导电层; 在导电叠层的侧壁上形成绝缘间隔层; 形成绝缘层; 形成覆盖所述绝缘层的部分的覆盖绝缘层; 以及形成填充接触孔以接触半导体衬底的导电焊盘。 封盖绝缘层具有缓冲器的功能，因此绝缘导电层的掩模层的蚀刻量最小化，电容器电极和导电叠层之间的短路的可能性大大降低。

公开(公告)号：US06967150B2

公开(公告)日：2005-11-22

申请号：US10938154

申请日：2004-09-10

Applicant: Cheol-Ju Yun ,  Tae-Young Chung

Inventor： Cheol-Ju Yun ,  Tae-Young Chung

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242

CPC classification number: H01L27/10885 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76897 ,  H01L27/10855

Abstract: According to some embodiments of the invention, a method of forming a self-aligned contact of a semiconductor device includes forming a plurality of conductive lines that are spaced apart from each other and pass over a plurality of conductive regions. An insulating layer is formed over and between the conductive lines. A plurality of contact holes are then formed to selectively expose the conductive regions by selectively removing the insulating layer without exposing the conductive lines. The contact holes are extended using an isotropic etching until the conductive lines begin to be exposed. Thereafter, contacts are formed in the contact holes such that the contacts are coupled to the conductive regions.

Abstract translation: 根据本发明的一些实施例，形成半导体器件的自对准接触的方法包括形成彼此间隔开并跨越多个导电区域的多条导线。 在导线之间和之间形成绝缘层。 然后形成多个接触孔，以通过选择性地去除绝缘层而不暴露导电线来选择性地暴露导电区域。 使用各向同性蚀刻使接触孔延伸，直到导线开始暴露。 此后，在接触孔中形成触点，使得触点耦合到导电区域。

公开(公告)号：US20050218439A1

公开(公告)日：2005-10-06

申请号：US11143197

申请日：2005-06-01

Applicant: Jae-Goo Lee ,  Cheol-Ju Yun

Inventor： Jae-Goo Lee ,  Cheol-Ju Yun

IPC: H01L21/768 ,  H01L21/4763 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76

CPC classification number: H01L27/10888 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885

Abstract: Bit lines having first conductive patterns and bit line mask patterns are formed on a first insulating layer between capacitor contact regions of a substrate. An oxide second insulating layer is formed on the bit lines and contact patterns are formed to open storage node contact hole regions corresponding to portions of the second insulating layer. First spacers are formed on sidewalls of the etched portions. The second and first insulating layers are etched to form storage node contact holes exposing the capacitor contact regions. Simultaneously, second spacers of the second insulating layer are formed beneath the first spacers. A second conductive layer fills the storage node contact holes to form storage node contact pads. A loss of the bit line mask pattern decreases due to the reduced thickness of the bit line mask pattern and a bit line loading capacitance decreases due to the second spacers.

Abstract translation: 具有第一导电图案和位线掩模图案的位线形成在衬底的电容器接触区域之间的第一绝缘层上。 在位线上形成氧化物第二绝缘层，并且形成接触图案以打开与第二绝缘层的部分相对应的存储节点接触孔区域。 在蚀刻部分的侧壁上形成第一间隔物。 蚀刻第二和第一绝缘层以形成暴露电容器接触区域的存储节点接触孔。 同时，第二绝缘层的第二间隔件形成在第一间隔件下面。 第二导电层填充存储节点接触孔以形成存储节点接触焊盘。 由于位线掩模图案的厚度减小，位线掩模图案的损失减小，并且位线负载电容由于第二间隔件而减小。

公开(公告)号：US06635582B2

公开(公告)日：2003-10-21

申请号：US09270229

申请日：1999-03-15

Applicant: Cheol-ju Yun ,  Young-min Kwon ,  Heung-soo Park

Inventor： Cheol-ju Yun ,  Young-min Kwon ,  Heung-soo Park

IPC: H01L21302

CPC classification number: H01L21/02071 ,  G03F7/422 ,  H01L21/76838

Abstract: A pre-stripping treatment solution for treatment of metal surfaces before stripping photoresist which has been used for patterning a metal layer. Also provided is a method of removing the photoresist, and a method of manufacturing semiconductor devices using the above solution and method. In one aspect of the invention, the photoresist is first ashed. The ashed resultant structure is then treated, prior to stripping of the photoresist, with a pre-stripping treatment solution of an organic acid solution having a carboxyl group is mixed with deionized water at a volume ratio of 1:0 to 1:100.

Abstract translation: 用于在剥离已经用于图案化金属层的光致抗蚀剂之前处理金属表面的预剥离处理溶液。 还提供了去除光致抗蚀剂的方法，以及使用上述溶液和方法制造半导体器件的方法。 在本发明的一个方面，首先将光致抗蚀剂灰化。 然后在剥离光致抗蚀剂之前，将具有羧基的有机酸溶液的预剥离处理溶液以1：0至1：100的体积比与去离子水混合，然后处理灰化的所得结构。

公开(公告)号：US07488644B2

公开(公告)日：2009-02-10

申请号：US11751515

申请日：2007-05-21

Applicant: Jae-Goo Lee ,  Cheol-Ju Yun

Inventor： Jae-Goo Lee ,  Cheol-Ju Yun

IPC: H01L21/8242

CPC classification number: H01L27/10888 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885

Abstract: Bit lines having first conductive patterns and bit line mask patterns are formed on a first insulating layer between capacitor contact regions of a substrate. An oxide second insulating layer is formed on the bit lines and contact patterns are formed to open storage node contact hole regions corresponding to portions of the second insulating layer. First spacers are formed on sidewalls of the etched portions. The second and first insulating layers are etched to form storage node contact holes exposing the capacitor contact regions. Simultaneously, second spacers of the second insulating layer are formed beneath the first spacers. A second conductive layer fills the storage node contact holes to form storage node contact pads. A loss of the bit line mask pattern decreases due to the reduced thickness of the bit line mask pattern and a bit line loading capacitance decreases due to the second spacers.

Abstract translation: 具有第一导电图案和位线掩模图案的位线形成在衬底的电容器接触区域之间的第一绝缘层上。 在位线上形成氧化物第二绝缘层，并且形成接触图案以打开与第二绝缘层的部分相对应的存储节点接触孔区域。 在蚀刻部分的侧壁上形成第一间隔物。 蚀刻第二和第一绝缘层以形成暴露电容器接触区域的存储节点接触孔。 同时，第二绝缘层的第二间隔件形成在第一间隔件下面。 第二导电层填充存储节点接触孔以形成存储节点接触焊盘。 由于位线掩模图案的厚度减小，位线掩模图案的损失减小，并且位线负载电容由于第二间隔件而减小。

公开(公告)号：US07388243B2

公开(公告)日：2008-06-17

申请号：US11430036

申请日：2006-05-09

Applicant: Cheol-Ju Yun ,  Chang-Hyun Cho ,  Tae-Young Chung

Inventor： Cheol-Ju Yun ,  Chang-Hyun Cho ,  Tae-Young Chung

IPC: H01L27/108

CPC classification number: H01L21/76897 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L28/91

Abstract: A self-aligned buried contact (BC) pair includes a substrate having diffusion regions; an oxide layer exposing a pair of diffusion regions formed on the substrate; bit lines formed between adjacent diffusion regions and on the oxide layer, each of the bit lines having bit line sidewall spacers formed on sidewalls thereof; a first interlayer dielectric (ILD) layer formed over the bit lines and the oxide layer; a pair of BC pads formed between adjacent bit lines and within the first ILD layer, each BC pad being aligned with one of the pair of exposed diffusion regions in the substrate; and a pair of capacitors, each of the pair of BC pads having one of the pair of capacitors formed thereon, wherein a pair of the bit line sidewall spacers is adjacent to each of the BC pads and the pair of bit line sidewall spacers has an asymmetrical shape.

Abstract translation: 自对准埋层接触（BC）对包括具有扩散区域的衬底; 暴露形成在所述基板上的一对扩散区域的氧化物层; 在相邻扩散区之间和氧化物层上形成的位线，每个位线在其侧壁上形成有位线侧壁间隔物; 形成在位线和氧化物层上的第一层间电介质（ILD）层; 一对BC焊盘，形成在相邻位线之间并且在第一ILD层内，每个BC焊盘与衬底中一对暴露的扩散区域中的一个对准; 和一对电容器，所述一对BC焊盘中的每一对具有形成在其上的一对电容器中的一个，其中一对位线侧壁间隔件与每个BC焊盘相邻，并且所述一对位线侧壁间隔件具有 不对称形状。

公开(公告)号：US07326613B2

公开(公告)日：2008-02-05

申请号：US11096129

申请日：2005-03-31

Applicant: Cheol-ju Yun ,  Tae-young Chung ,  Dong-jun Lee

Inventor： Cheol-ju Yun ,  Tae-young Chung ,  Dong-jun Lee

IPC: H01L21/8242

CPC classification number: H01L27/10888 ,  H01L21/76804 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10891

Abstract: A method of manufacturing a semiconductor device includes forming conductive structures on a substrate. Each of the conductive structures has a line shape that extends along a first direction parallel to the substrate. Insulating spacers are formed on upper sidewalls of the conductive structures. An insulating interlayer is formed that covers the conductive structures. A portion of the insulating interlayer between the conductive structures is etched to form a contact hole. An upper portion of the contact hole is larger than a lower portion thereof. The upper portion of the contact hole has a first width along the first direction and a second width along a second direction parallel to the substrate and substantially perpendicular to the first direction. The first width is substantially larger than the second width. The contact hole is filled with a conductive material to form a contact plug.

Abstract translation: 制造半导体器件的方法包括在衬底上形成导电结构。 每个导电结构具有沿平行于基板的第一方向延伸的线状。 绝缘垫片形成在导电结构的上侧壁上。 形成覆盖导电结构的绝缘中间层。 导电结构之间的绝缘中间层的一部分被蚀刻以形成接触孔。 接触孔的上部大于其下部。 接触孔的上部具有沿着第一方向的第一宽度和沿着平行于基底并基本上垂直于第一方向的第二方向的第二宽度。 第一宽度基本上大于第二宽度。 接触孔填充有导电材料以形成接触塞。

公开(公告)号：US20080014695A1

公开(公告)日：2008-01-17

申请号：US11769276

申请日：2007-06-27

Applicant: Jin-Woo Lee ,  Cheol-Ju Yun ,  Hyeoung-Won Seo

Inventor： Jin-Woo Lee ,  Cheol-Ju Yun ,  Hyeoung-Won Seo

IPC: H01L21/8242 ,  H01L21/336

CPC classification number: H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L28/91 ,  H01L29/6659

Abstract: A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impurity region formed in the semiconductor pattern and at surface portions of the substrate, respectively, wherein the first and second impurity regions include a first conductive type impurity, and a channel doping region surrounding the first impurity region, wherein the channel doping region includes a second conductive type impurity.

Abstract translation: 半导体器件包括形成在衬底上的多个栅极结构，形成在栅极结构的侧壁上的栅极间隔物，形成在栅极结构之间的衬底上的半导体图案，形成在栅极结构中的第一杂质区域和第二杂质区域 半导体图案和衬底的表面部分，其中第一和第二杂质区域包括第一导电类型杂质和围绕第一杂质区的沟道掺杂区域，其中沟道掺杂区域包括第二导电类型杂质。

公开(公告)号：US20070278548A1

公开(公告)日：2007-12-06

申请号：US11769260

申请日：2007-06-27

Applicant: Jin-Woo Lee ,  Cheol-Ju Yun ,  Hyeoung-Won Seo

Inventor： Jin-Woo Lee ,  Cheol-Ju Yun ,  Hyeoung-Won Seo

IPC: H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L28/91 ,  H01L29/6659

Abstract: A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impurity region formed in the semiconductor pattern and at surface portions of the substrate, respectively, wherein the first and second impurity regions include a first conductive type impurity, and a channel doping region surrounding the first impurity region, wherein the channel doping region includes a second conductive type impurity.

Abstract translation: 半导体器件包括形成在衬底上的多个栅极结构，形成在栅极结构的侧壁上的栅极间隔物，形成在栅极结构之间的衬底上的半导体图案，形成在栅极结构中的第一杂质区域和第二杂质区域 半导体图案和衬底的表面部分，其中第一和第二杂质区域包括第一导电类型杂质和围绕第一杂质区的沟道掺杂区域，其中沟道掺杂区域包括第二导电类型杂质。

公开(公告)号：US07078292B2

公开(公告)日：2006-07-18

申请号：US10875004

申请日：2004-06-22

Applicant: Je-Min Park ,  Yoo-Sang Hwang ,  Cheol-Ju Yun

Inventor： Je-Min Park ,  Yoo-Sang Hwang ,  Cheol-Ju Yun

IPC: H01L21/8242

CPC classification number: H01L27/10855 ,  H01L27/10814 ,  H01L28/91

Abstract: A storage node contact forming method and structure reduces the number of processes required by the conventional art and increases a critical dimension of a storage node to prevent a leaning phenomenon and reduce a manufacturing cost of semiconductor memory devices. The method includes preparing a semiconductor substrate that involves at least one contact pad contacted with an active region of a memory cell transistor through an insulation layer. The method also includes forming a storage node contact of T-shape, the storage node contact being composed of a lower region contacted with an upper part of the contact pad, and an upper region that is extended to a gate length direction of the memory cell transistor and that is formed as a size larger than a size of the lower region, in order to electrically connect the contact pad with a storage node to be formed in a later process.

Abstract translation: 存储节点接触形成方法和结构减少了传统技术所需的处理次数，并且增加了存储节点的临界尺寸以防止倾斜现象并降低半导体存储器件的制造成本。 该方法包括制备半导体衬底，其包括通过绝缘层与存储单元晶体管的有源区接触的至少一个接触焊盘。 该方法还包括形成T形的存储节点接触，所述存储节点接触由与所述接触焊盘的上部接触的下部区域和延伸到所述存储单元的栅极长度方向的上部区域 晶体管，并且形成为大于下部区域的尺寸的尺寸，以便将接触焊盘与要在稍后的工艺中形成的存储节点电连接。