公开(公告)号：US07253758B2

公开(公告)日：2007-08-07

申请号：US11185287

申请日：2005-07-20

申请人： Long-Xi Chang ,  Chia-Chun Hung

发明人： Long-Xi Chang ,  Chia-Chun Hung

IPC分类号： H03M3/00

CPC分类号： H03M3/448 ,  H03M3/424 ,  H03M3/454 ,  H03M7/3026 ,  H03M7/3035

摘要： A third order sigma-delta modulator comprises a first summing unit for receiving an input signal, a first integrator network connected to an output of the first summing unit, a second integrator network for receiving an output of the first integrator network, a second summing unit connected to an output of the second integrator network, a third integrator network connected to an output of the second summing unit, and a feed-forward path from the output of the first integrator network to an input of the second summing unit.

公开(公告)号：US07233050B2

公开(公告)日：2007-06-19

申请号：US11419866

申请日：2006-05-23

申请人： Wei Zhang ,  Chian-Liang Lin ,  Jung-Chen Yang ,  Chia-Chun Hung ,  Shih-Min Liu

发明人： Wei Zhang ,  Chian-Liang Lin ,  Jung-Chen Yang ,  Chia-Chun Hung ,  Shih-Min Liu

IPC分类号： H01L31/0203

CPC分类号： H01L27/14689 ,  H01L27/14609 ,  H01L27/14687

摘要： A method is disclosed for forming at least one image sensor with improved sensitivity along with at least one transistor device. The method comprises forming at least a portion of the transistor device on a substrate, forming the image sensor by doping a predetermined area separated from the transistor device by a minimum predetermined distance, forming an etch stop layer for covering a contact area of the transistor device, removing at least a portion of the etch stop layer in the predetermined area for exposing the image sensor, and covering the image sensor and the transistor device by at least one transparent protection layer.

摘要翻译： 公开了一种用于与至少一个晶体管器件一起形成具有改进的灵敏度的至少一个图像传感器的方法。 该方法包括在衬底上形成晶体管器件的至少一部分，通过将与晶体管器件分离的预定区域掺杂最小预定距离来形成图像传感器，形成用于覆盖晶体管器件的接触区域的蚀刻停止层 在所述预定区域中去除所述蚀刻停止层的至少一部分以暴露所述图像传感器，以及通过至少一个透明保护层覆盖所述图像传感器和所述晶体管器件。

公开(公告)号：US20100122139A1

公开(公告)日：2010-05-13

申请号：US12613059

申请日：2009-11-05

申请人： Cheng-Kang WANG ,  Hou-Wei LIN ,  Chia-Chun HUNG

发明人： Cheng-Kang WANG ,  Hou-Wei LIN ,  Chia-Chun HUNG

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/1122 ,  H03M13/112 ,  H04L1/0045 ,  H04L1/0057

摘要： A parity-check-code decoder is adapted for receiving a channel quality ratio and at least (N) bits that are to be decoded. The parity-check-code decoder treats each of the bits as a bit node, and includes: a verifying circuit that multiplies (N) bit nodes by a matrix to obtain (N-K) check nodes; a reliability-generating circuit that generates a reliability index that serves as an extrinsic check index for each of the bit nodes to transmit to the check nodes; a bit exchange circuit that generates an extrinsic bit index for each of the check nodes to transmit to the bit nodes; a check-exchange circuit that updates a plurality of the extrinsic check indices based on the extrinsic bit indices for the bit nodes to transmit to the check nodes; and a reliability-updating circuit that updates the reliability index of and determines an updated value for each of the bit nodes.

摘要翻译： 奇偶校验码解码器适于接收信道质量比和要被解码的至少（N）个比特。 奇偶校验码解码器将每个比特作为比特节点处理，并且包括：验证电路，用（N）比特节点乘以矩阵来获得（N-K）个校验节点; 可靠性产生电路，其生成作为用于每个位节点的外部检查指标的可靠性指标，以向所述校验节点发送; 一个位交换电路，用于为每个校验节点产生一个外在比特索引，以传送给比特节点; 检查交换电路，其基于所述比特节点的所述外在比特索引更新所述外部校验索引，以向所述校验节点发送; 以及可靠性更新电路，其更新每个位节点的可靠性指标并确定更新的值。

公开(公告)号：US07158093B2

公开(公告)日：2007-01-02

申请号：US11079284

申请日：2005-03-15

申请人： Pei-Lin Yang ,  Chia-Chun Hung ,  Chun-Hao Chen ,  Ting-Chun Lee

发明人： Pei-Lin Yang ,  Chia-Chun Hung ,  Chun-Hao Chen ,  Ting-Chun Lee

IPC分类号： H01Q1/36

CPC分类号： H01Q1/38 ,  H01Q1/362 ,  H01Q11/08

摘要： The present invention discloses a quadri-filar helix antenna structure, which comprises a cylindrical body made of a dielectric material with a relative dielectric constant ∈r greater than 4, and four radiating metal plates disposed on a distal end surface of the cylindrical body and extended along the radial direction of the center of the cylindrical body to its periphery and then along the radial direction in a spiral course on the circumferential surface thereof to its periphery on the other end respectively, wherein the ends of every two adjacent radiating metal plates are coupled with each other to constitute two sets of antenna structures, a penetrating hole is disposed at the central position of the cylindrical body and is precisely embedded into a coaxial cable, and a shield cable disposed at the periphery on one end of the coaxial cable is coupled to an end of another set of antenna structure. Therefore, the antenna not only reduces the overall volume, but also greatly lowers its production costs.

摘要翻译： 本发明公开了一种四线螺旋天线结构，其包括由相对介电常数εζ大于4的电介质材料制成的圆柱体，以及设置在远端上的四个辐射金属板 圆柱体的表面并沿着圆柱体的中心的径向方向延伸到其周边，然后沿其径向方向在其圆周表面上以螺旋状的方式延伸到另一端的周边，其中每个 两个相邻的辐射金属板彼此耦合以构成两组天线结构，在圆柱体的中心位置设置一个穿透孔，并且精确地嵌入到同轴电缆中，并且屏蔽电缆设置在一个外围的一个 同轴电缆的端部耦合到另一组天线结构的一端。 因此，天线不仅可以降低总体积，而且大大降低了其生产成本。

公开(公告)号：US07071019B2

公开(公告)日：2006-07-04

申请号：US10944243

申请日：2004-09-16

申请人： Wei Zhang ,  Chian-Liang Lin ,  Jung-Chen Yang ,  Chia-Chun Hung ,  Shih-Min Liu

发明人： Wei Zhang ,  Chian-Liang Lin ,  Jung-Chen Yang ,  Chia-Chun Hung ,  Shih-Min Liu

IPC分类号： H01L21/00

CPC分类号： H01L27/14689 ,  H01L27/14609 ,  H01L27/14687

摘要： A method is disclosed for forming at least one image sensor with improved sensitivity along with at least one transistor device. The method comprises forming at least a portion of the transistor device on a substrate, forming the image sensor by doping a predetermined area separated from the transistor device by a minimum predetermined distance, forming an etch stop layer for covering a contact area of the transistor device, removing at least a portion of the etch stop layer in the predetermined area for exposing the image sensor, and covering the image sensor and the transistor device by at least one transparent protection layer.

公开(公告)号：US09345634B2

公开(公告)日：2016-05-24

申请号：US13620406

申请日：2012-09-14

申请人： Ming-Shaung Ju ,  Chou-Ching Lin ,  Meng-Dar Shieh ,  Shu-Min Chen ,  Yu-Ching Lin ,  Yung-Nien Sun ,  Pin-Cheng Kung ,  Chia-Chun Hung ,  Yi-Ting Lee

发明人： Ming-Shaung Ju ,  Chou-Ching Lin ,  Meng-Dar Shieh ,  Shu-Min Chen ,  Yu-Ching Lin ,  Yung-Nien Sun ,  Pin-Cheng Kung ,  Chia-Chun Hung ,  Yi-Ting Lee

IPC分类号： A61H1/00 ,  A61H1/02

CPC分类号： A61H1/0285 ,  A61H1/0288 ,  A61H2201/0157 ,  A61H2201/123 ,  A61H2201/1246 ,  A61H2201/1638 ,  A61H2201/1676

摘要： A hand rehabilitation device includes a base having an arm support. A first actuator is mounted to the base and includes a first output end. A second actuator is connected to the first output end of the first actuator and includes a second output end. A handle is connected to the second output end. One of the first and second output ends rotates about an axis. The other of the first and second output ends reciprocates in a direction.

摘要翻译： 手部康复装置包括具有手臂支撑件的底座。 第一致动器安装到基座并且包括第一输出端。 第二致动器连接到第一致动器的第一输出端并且包括第二输出端。 手柄连接到第二输出端。 第一和第二输出端中的一个绕轴旋转。 第一和第二输出端中的另一个在一个方向上往复运动。

公开(公告)号：US20070018865A1

公开(公告)日：2007-01-25

申请号：US11185287

申请日：2005-07-20

申请人： Long-Xi Chang ,  Chia-Chun Hung

发明人： Long-Xi Chang ,  Chia-Chun Hung

IPC分类号： H03M3/00

CPC分类号： H03M3/448 ,  H03M3/424 ,  H03M3/454 ,  H03M7/3026 ,  H03M7/3035

摘要： A third order sigma-delta modulator comprises a first summing unit for receiving an input signal, a first integrator network connected to an output of the first summing unit, a second integrator network for receiving an output of the first integrator network, a second summing unit connected to an output of the second integrator network, a third integrator network connected to an output of the second summing unit, and a feed-forward path from the output of the first integrator network to an input of the second summing unit.

摘要翻译： 第三级Σ-Δ调制器包括用于接收输入信号的第一求和单元，连接到第一求和单元的输出的第一积分器网络，用于接收第一积分器网络的输出的第二积分器网络，第二加法单元 连接到第二积分器网络的输出，连接到第二求和单元的输出的第三积分器网络，以及从第一积分器网络的输出到第二求和单元的输入的前馈路径。

公开(公告)号：US20060057759A1

公开(公告)日：2006-03-16

申请号：US10944243

申请日：2004-09-16

申请人： Wei Zhang ,  Chian-Liang Lin ,  Jung-Chen Yang ,  Chia-Chun Hung ,  Shih-Min Liu

发明人： Wei Zhang ,  Chian-Liang Lin ,  Jung-Chen Yang ,  Chia-Chun Hung ,  Shih-Min Liu

IPC分类号： H01L21/00

CPC分类号： H01L27/14689 ,  H01L27/14609 ,  H01L27/14687

摘要： A method is disclosed for forming at least one image sensor with improved sensitivity along with at least one transistor device. The method comprises forming at least a portion of the transistor device on a substrate, forming the image sensor by doping a predetermined area separated from the transistor device by a minimum predetermined distance, forming an etch stop layer for covering a contact area of the transistor device, removing at least a portion of the etch stop layer in the predetermined area for exposing the image sensor, and covering the image sensor and the transistor device by at least one transparent protection layer.

摘要翻译： 公开了一种用于与至少一个晶体管器件一起形成具有改进的灵敏度的至少一个图像传感器的方法。 该方法包括在衬底上形成晶体管器件的至少一部分，通过将与晶体管器件分离的预定区域掺杂最小预定距离来形成图像传感器，形成用于覆盖晶体管器件的接触区域的蚀刻停止层 在所述预定区域中去除所述蚀刻停止层的至少一部分以暴露所述图像传感器，以及通过至少一个透明保护层覆盖所述图像传感器和所述晶体管器件。

公开(公告)号：US08572452B2

公开(公告)日：2013-10-29

申请号：US12567558

申请日：2009-09-25

申请人： Cheng-Kang Wang ,  Chun-Ming Cho ,  Chia Chun Hung

发明人： Cheng-Kang Wang ,  Chun-Ming Cho ,  Chia Chun Hung

IPC分类号： H03M13/00

CPC分类号： H03M13/13 ,  H03M13/451 ,  H03M13/6502

摘要： A block code decoding method and device thereof are provided. The procedure of the bounded distance decoding is simplified and the number of correlation calculating is reduced via a set of pre-established XOR masks. The decoding method includes: picking up the source code part of the received message; executing a XOR calculating for the source code part with the XOR masks, and encoding the results thereof to produce a set of compared codes; executing a correlation calculating for the set of compared codes and the received message; and determining a compared code having the maximum correlation result as the decision.

摘要翻译： 提供了一种块码解码方法及其装置。 有限距离解码的过程被简化，并且通过一组预先建立的XOR掩模减少了相关计算的数量。 解码方法包括：拾取接收到的消息的源代码部分; 使用XOR掩码对源代码部分执行XOR计算，并对其结果进行编码以产生一组比较的代码; 对所述一组比较代码和所接收的消息执行相关性计算; 以及确定具有最大相关结果的比较代码作为所述决定。

公开(公告)号：US08527857B2

公开(公告)日：2013-09-03

申请号：US12613059

申请日：2009-11-05

申请人： Cheng-Kang Wang ,  Hou-Wei Lin ,  Chia-Chun Hung

发明人： Cheng-Kang Wang ,  Hou-Wei Lin ,  Chia-Chun Hung

IPC分类号： G06F11/00

CPC分类号： H03M13/1122 ,  H03M13/112 ,  H04L1/0045 ,  H04L1/0057

摘要： A parity-check-code decoder is adapted for receiving a channel quality ratio and at least (N) bits that are to be decoded. The parity-check-code decoder treats each of the bits as a bit node, and includes: a verifying circuit that multiplies (N) bit nodes by a matrix to obtain (N-K) check nodes; a reliability-generating circuit that generates a reliability index that serves as an extrinsic check index for each of the bit nodes to transmit to the check nodes; a bit exchange circuit that generates an extrinsic bit index for each of the check nodes to transmit to the bit nodes; a check-exchange circuit that updates a plurality of the extrinsic check indices based on the extrinsic bit indices for the bit nodes to transmit to the check nodes; and a reliability-updating circuit that updates the reliability index of and determines an updated value for each of the bit nodes.

摘要翻译： 奇偶校验码解码器适于接收信道质量比和要被解码的至少（N）个比特。 奇偶校验码解码器将每个比特作为比特节点处理，并且包括：验证电路，用（N）比特节点乘以矩阵来获得（N-K）个校验节点; 可靠性产生电路，其生成作为用于每个位节点的外部检查指标的可靠性指标，以向所述校验节点发送; 一个位交换电路，用于为每个校验节点产生一个外在比特索引，以传送给比特节点; 检查交换电路，其基于所述比特节点的所述外在比特索引更新所述外部校验索引，以向所述校验节点发送; 以及可靠性更新电路，其更新每个位节点的可靠性指标并确定更新的值。