公开(公告)号：US5045483A

公开(公告)日：1991-09-03

申请号：US503340

申请日：1990-04-02

申请人： Bancherd DeLong ,  Christopher S. Blair ,  George E. Ganschow ,  Thomas S. Crabb

发明人： Bancherd DeLong ,  Christopher S. Blair ,  George E. Ganschow ,  Thomas S. Crabb

IPC分类号： H01L21/02 ,  H01L21/285 ,  H01L21/331

CPC分类号： H01L28/20 ,  H01L21/28525 ,  H01L29/66272 ,  H01L29/6628 ,  Y10S148/123

摘要： A bipolar transistor and resistor are provided. Fabrication includes using a high temperature oxide to form sidewall spacers for the transistor contacts and/or to overlay the resistor portion of the device. Deposition of the HTO is combined with dopant drive-in so that fewer total steps are required. The process is compatible with MOS technology so that the bipolar transistor and resistor can be formed on a substrate along with MOS devices.

公开(公告)号：US08624349B1

公开(公告)日：2014-01-07

申请号：US12901924

申请日：2010-10-11

申请人： Christopher S Blair

发明人： Christopher S Blair

IPC分类号： H01L21/70

CPC分类号： H01L29/0649 ,  H01L21/76283

摘要： Techniques are described to simultaneously form an isolation trench and a handle wafer contact without additional mask steps. In one or more implementations, an isolation trench and a handle wafer contact trench are simultaneously formed in a substrate. The substrate includes an insulating layer that defines a trench bottom of the handle wafer contact trench. A handle wafer is bonded to a bottom surface of the substrate. An oxide insulating layer is deposited in the isolation trench and the handle wafer contact trench. The oxide insulating layer is then etched so that the oxide insulating layer covering the trench bottom is at least partially removed. The trench bottom is then etched so that a top surface of the handle wafer is at least partially exposed. The handle wafer contact trench may then be at least partially filled with an electrical conductive material.

摘要翻译： 描述了技术以同时形成隔离沟槽和处理晶片接触，而无需额外的掩模步骤。 在一个或多个实施方案中，在衬底中同时形成隔离沟槽和处理晶片接触沟槽。 衬底包括限定处理晶片接触沟槽的沟槽底部的绝缘层。 把手晶片结合到衬底的底表面。 氧化物绝缘层沉积在隔离沟槽和处理晶片接触沟槽中。 然后蚀刻氧化物绝缘层，使得覆盖沟槽底部的氧化物绝缘层至少部分地被去除。 然后蚀刻沟槽底部，使得处理晶片的顶表面至少部分地暴露。 处理晶片接触沟槽然后可以至少部分地填充有导电材料。

公开(公告)号：US06171901B2

公开(公告)日：2001-01-09

申请号：US09356012

申请日：1999-07-16

申请人： Christopher S. Blair ,  Weidong Chen

发明人： Christopher S. Blair ,  Weidong Chen

IPC分类号： H01L218242

CPC分类号： H01L28/60 ,  H01L21/3144 ,  H01L21/32105 ,  H01L27/0629

摘要： A process flow for forming a polysilicon-to-polysilicon capacitor performs the capacitor anneal step in a nitrous oxide ambient. As a result, a nitroxide layer forms over heavily doped polysilicon of the upper electrode of the capacitor. This nitroxide layer acts as a barrier against the diffusion of oxygen, preventing further oxidation of the heavily doped polysilicon electrode layer during the subsequent seal oxidation step. The nitroxide barrier layer is readily removed along with the other seal oxide layers immediately before formation of the silicided capacitor electrode contacts, without any attendant danger of overetching of gate oxide or spacer structures. Where the gate polysilicon layer is doped immediately after its formation, an additional capacitor anneal step in a nitrous oxide ambient is necessary to form an additional nitroxide layer.

摘要翻译： 用于形成多晶硅至多晶硅电容器的工艺流程在一氧化二氮环境中执行电容器退火步骤。 结果，在电容器的上电极的重掺杂多晶硅上形成氮氧化物层。 该氮氧化物层用作抵抗氧的扩散的阻挡层，防止在随后的密封氧化步骤期间重掺杂多晶硅电极层的进一步氧化。 在形成硅化物电容器电极接触之前，氮氧化物阻挡层与其他密封氧化物层一起容易除去，而不会过度腐蚀栅极氧化物或间隔物结构的危险。 在栅极多晶硅层在其形成之后立即被掺杂的情况下，在一氧化氮环境中需要额外的电容器退火步骤以形成另外的氮氧化物层。

公开(公告)号：US5451546A

公开(公告)日：1995-09-19

申请号：US209087

申请日：1994-03-10

申请人： Michael J. Grubisich ,  Christopher S. Blair

发明人： Michael J. Grubisich ,  Christopher S. Blair

IPC分类号： H01L21/768 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L21/768 ,  H01L21/76889

摘要： A masking method for use in a silicide formation process is disclosed herein which prevents an oxide etching solution from tunneling under a photoresist masking layer and damaging oxide spacers not intended to be etched. This process may be used during the formation of a bipolar or MOS transistor formed in an isolated silicon island. A mask opening used to etch exposed oxide spacer portions is made to not expose any parasitic oxide spacers formed along an edge of the isolated silicon island. In this way, an oxide etch solution is prevented from tunneling along the parasitic oxide spacer and reaching any intersecting oxide spacers not intended to be etched. The desired oxide spacers will thus be intact to properly isolate silicide portions formed over exposed silicon and polysilicon surfaces.

摘要翻译： 本文公开了一种在硅化物形成工艺中使用的掩模方法，其防止氧化物蚀刻溶液在光致抗蚀剂掩模层下方隧穿并损坏不想蚀刻的氧化物间隔物。 该过程可以在形成在隔离硅岛中形成的双极或MOS晶体管时使用。 用于蚀刻暴露的氧化物间隔物部分的掩模开口被制成不暴露沿隔离的硅岛的边缘形成的任何寄生氧化物间隔物。 以这种方式，防止氧化物蚀刻溶液沿着寄生氧化物间隔物隧道化并到达任何不想蚀刻的相交氧化物间隔物。 因此，期望的氧化物间隔物将是完整的，以适当地隔离在暴露的硅和多晶硅表面上形成的硅化物部分。

公开(公告)号：US5242854A

公开(公告)日：1993-09-07

申请号：US879650

申请日：1992-05-07

申请人： Alan G. Solheim ,  Christopher S. Blair ,  Vida Ilderem ,  Ali A. Iranmanesh

发明人： Alan G. Solheim ,  Christopher S. Blair ,  Vida Ilderem ,  Ali A. Iranmanesh

IPC分类号： H01L21/285 ,  H01L21/32 ,  H01L21/331 ,  H01L21/762 ,  H01L29/732

CPC分类号： H01L29/6628 ,  H01L21/28525 ,  H01L21/32 ,  H01L21/76205 ,  H01L29/732

摘要： A high performance bipolar transistor and a method of fabrication. Base resistance is reduced by a self-aligned silicide formed in the single-crystal region of the extrinsic base, thereby eliminating the polysilicon to single-crystal contact resistance as well as shunting the resistance of the single-crystal extrinsic base region. Oxide from the sidewall of the polysilicon local interconnection is selectively removed prior to silicide formation. Therefore, selected sidewalls of the poly interconnect layer also becomes silicided. This results in significant reductions in resistance of the interconnection, particularly for submicron geometries. Improved techniques for forming field oxide regions and for forming base regions of bipolar transistors are also disclosed.

摘要翻译： 高性能双极晶体管及其制造方法。 通过在外部基极的单晶区域中形成的自对准硅化物来降低基极电阻，从而消除多晶硅到单晶接触电阻以及分流单晶非本征基极区域的电阻。 在硅化物形成之前，选择性地去除来自多晶硅局部互连的侧壁的氧化物。 因此，多晶硅互连层的选定侧壁也变成硅化物。 这导致互连电阻的显着降低，特别是对于亚微米几何形状。 还公开了用于形成场氧化物区域和用于形成双极晶体管的基极区域的改进的技术。

公开(公告)号：US5139961A

公开(公告)日：1992-08-18

申请号：US503498

申请日：1990-04-02

申请人： Alan G. Solheim ,  Bamdad Bastani ,  James L. Bouknight ,  George E. Ganschow ,  Bancherd Delong ,  Rajeeva Lahri ,  Steve M. Leibiger ,  Christopher S. Blair ,  Rick C. Jerome ,  Madan Biswal ,  Tad Davies ,  Vida Ilderem ,  Ali A. Iranmanesh

发明人： Alan G. Solheim ,  Bamdad Bastani ,  James L. Bouknight ,  George E. Ganschow ,  Bancherd Delong ,  Rajeeva Lahri ,  Steve M. Leibiger ,  Christopher S. Blair ,  Rick C. Jerome ,  Madan Biswal ,  Tad Davies ,  Vida Ilderem ,  Ali A. Iranmanesh

IPC分类号： H01L29/73 ,  H01L21/285 ,  H01L21/32 ,  H01L21/331 ,  H01L21/762 ,  H01L29/732

CPC分类号： H01L29/6628 ,  H01L21/28525 ,  H01L21/32 ,  H01L21/76205 ,  H01L29/732 ,  Y10S148/01

摘要： A high performance bipolar transistor and a method of fabrication. Base resistance is reduced by a self-aligned silicide formed in the single-crystal region of the extrinsic base, thereby eliminating the polysilicon to single-crystal contact resistance as well as shunting the resistance of the single-crystal extrinsic base region. Oxide from the sidewall of the polysilicon local interconnection is selectively removed prior to silicide formation. Therefore, selected sidewalls of the poly interconnect layer also becomes silicided. This results in significant reductions in resistance of the interconnection, particularly for sub-micron geometries. Improved techniques for forming field oxide regions and for forming base regions of bipolar transistors are also disclosed.

公开(公告)号：US6136705A

公开(公告)日：2000-10-24

申请号：US176785

申请日：1998-10-22

申请人： Christopher S. Blair

发明人： Christopher S. Blair

IPC分类号： H01L29/786 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/44

CPC分类号： H01L29/66575 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665

摘要： A process for the controlled formation of self-aligned dual thickness cobalt silicide layers during the manufacturing of a semiconductor device that requires a minimum number of steps and is compatible with standard MOS processing techniques. In the process according to the present invention, a semiconductor device structure (such as an MOS transistor) is first provided. The semiconductor device structure includes exposed silicon substrate surfaces (such as shallow drain and source regions) and a silicon layer structure disposed above the semiconductor substrate surface (such as a polysilicon gate). A cobalt layer is then deposited over the semiconductor device structure followed by the deposition of a titanium capping layer. Next, the thickness of the titanium capping layer above the silicon layer structure (e.g. a polysilicon gate) is selectively reduced using, for example, chemical mechanical polishing techniques. Cobalt from the cobalt layer is subsequently reacted with silicon from the exposed silicon substrate surfaces to form a first self-aligned cobalt silicide layer on these surfaces. At the same time, cobalt from the cobalt layer is reacted with silicon from the silicon layer structure to form a second self-aligned cobalt silicide layer thereon, which is thicker than the first self-aligned cobalt silicide layer.

摘要翻译： 在制造半导体器件期间可控制形成自对准双重厚度钴硅化物层的方法，其需要最小数量的步骤并与标准MOS处理技术兼容。 在根据本发明的方法中，首先提供半导体器件结构（诸如MOS晶体管）。 半导体器件结构包括暴露的硅衬底表面（例如浅漏极和源极区）以及设置在半导体衬底表面（例如多晶硅栅极）上方的硅层结构。 然后将钴层沉积在半导体器件结构上，随后沉积钛覆盖层。 接下来，使用例如化学机械抛光技术，选择性地降低硅层结构（例如多晶硅栅极）上方的钛覆盖层的厚度。 来自钴层的钴随后与来自暴露的硅衬底表面的硅反应，以在这些表面上形成第一自对准钴硅化物层。 同时，来自钴层的钴与来自硅层结构的硅反应，在其上形成比第一自对准硅化钴层厚的第二自对准硅化钴层。