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    Apparatus and method for generating a Galois-field syndrome
    11.
    发明授权
    Apparatus and method for generating a Galois-field syndrome 失效
    用于产生伽罗瓦氏综合征的装置和方法

    公开(公告)号：US07607068B2

    公开(公告)日：2009-10-20

    申请号：US11469222

    申请日：2006-08-31

    Applicant: Vinodh Gopal ,  Gilbert M. Wolrich ,  Daniel Cutter ,  Wajdi Feghali ,  Robert P. Ottavi

    Inventor： Vinodh Gopal ,  Gilbert M. Wolrich ,  Daniel Cutter ,  Wajdi Feghali ,  Robert P. Ottavi

    IPC: G11C29/00

    CPC classification number: G06F11/1076 ,  G06F2211/1054 ,  G06F2211/1057

    Abstract: The present disclosure provides an apparatus and method for generating a Galois-field syndrome. One exemplary method may include loading a first data byte from a first storage device to a first register and loading a second data byte from a second storage device to a second register; ANDing the most significant bit (MSB) of the first data byte and a Galois-field polynomial to generate a first intermediate output; XORing each bit of the first intermediate output with the least significant bits (LSBs) of the first data byte to generate a second intermediate output; MUXing the second intermediate output with each bit of the first data byte to generate a third intermediate output; XORing each bit of the third intermediate output with each bit of the second data byte to generate at a fourth intermediate output; and generating a RAID Q syndrome based on, at least in part, the fourth intermediate output. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

    Abstract translation: 本公开提供了一种用于产生伽罗瓦域综合征的装置和方法。 一个示例性方法可以包括将第一数据字节从第一存储设备加载到第一寄存器，并将第二数据字节从第二存储设备加载到第二寄存器; 将第一数据字节的最高有效位（MSB）和伽罗瓦域多项式进行比较以产生第一中间输出; 用第一数据字节的最低有效位（LSB）对第一中间输出的每个位进行异或，以产生第二中间输出; 将第二中间输出与第一数据字节的每个位进行多路复用以产生第三中间​​输出; 将第三中间输出的每个位与第二数据字节的每个位进行异或，以在第四中间输出处产生; 以及至少部分地基于第四中间输出产生RAID Q综合征。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

    Carry/Borrow Handling
    12.
    发明申请
    Carry/Borrow Handling 审中-公开
    携带/借款处理

    公开(公告)号：US20080148011A1

    公开(公告)日：2008-06-19

    申请号：US11610897

    申请日：2006-12-14

    Applicant: Vinodh Gopal ,  Gilbert M. Wolrich ,  Gunnar Gaubatz ,  Daniel Cutter ,  Wajdi Feghali ,  Kaan Yuksel ,  Erdinc Ozturk

    Inventor： Vinodh Gopal ,  Gilbert M. Wolrich ,  Gunnar Gaubatz ,  Daniel Cutter ,  Wajdi Feghali ,  Kaan Yuksel ,  Erdinc Ozturk

    IPC: G06F9/30

    CPC classification number: G06F9/3001

    Abstract: The present disclosure provides a system and method for performing carry/borrow handling. A method according to one embodiment may include generating a first result having a first carry or borrow from a first mathematical operation and storing the first carry or borrow and a first pointer address in a temporary register. The method may further include generating a second result having a second carry or borrow from a second mathematical operation and calling a subroutine configured to perform carry and borrow handling. The method may also include copying the first pointer address from the temporary register into a global variable. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

    Abstract translation: 本公开提供了用于执行进位/借用处理的系统和方法。 根据一个实施例的方法可以包括从第一数学运算产生具有第一进位或借位的第一结果，并将第一进位或借位以及第一指针地址存储在临时寄存器中。 该方法还可以包括从第二数学运算产生具有第二进位或借位的第二结果，并调用被配置为执行进位和借位处理的子程序。 该方法还可以包括将第一指针地址从临时寄存器复制到全局变量中。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

    SRAM controller for parallel processor architecture and method for controlling access to a RAM using read and read/write queues
    13.
    发明授权
    SRAM controller for parallel processor architecture and method for controlling access to a RAM using read and read/write queues 有权
    用于并行处理器架构的SRAM控制器和用于使用读取/读取队列控制对RAM的访问的方法

    公开(公告)号：US06728845B2

    公开(公告)日：2004-04-27

    申请号：US10208264

    申请日：2002-07-30

    Applicant: Matthew J. Adiletta ,  William Wheeler ,  James Redfield ,  Daniel Cutter ,  Gilbert Wolrich

    Inventor： Matthew J. Adiletta ,  William Wheeler ,  James Redfield ,  Daniel Cutter ,  Gilbert Wolrich

    IPC: G06F1300

    CPC classification number: G06F13/1642

    Abstract: A controller for a random access memory (RAM), such as a static ram (SRAM), includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues. The memory controller may be used in parallel processing systems and may also include an order queue, a lock lookup content addressable memory (CAM) and a read lock fail queue. A system including a media access controller (MAC), a network processor and an SRAM controller, and a method for controlling a RAM, are also described.

    Abstract translation: 用于诸如静态RAM（SRAM）的随机存取存储器（RAM）的控制器包括保存来自多个微控制器功能单元的存储器引用的地址和命令队列。 地址和命令队列包括存储读取存储器引用的读取队列。 控制器还包括第一读/写队列，其保存来自核心处理器的存储器引用和控制逻辑，所述控制逻辑包括检测每个队列的完整性的仲裁器以及尚未完成的存储器引用的完成状态以从以下之一中选择存储器引用 排队。 存储器控制器可以在并行处理系统中使用，并且还可以包括订单队列，锁定查找内容可寻址存储器（CAM）和读锁定失败队列。 还描述了包括媒体访问控制器（MAC），网络处理器和SRAM控制器的系统以及用于控制RAM的方法。

    Configurable Exponent Fifo
    18.
    发明申请
    Configurable Exponent Fifo 有权
    可配置指数

    公开(公告)号：US20080147768A1

    公开(公告)日：2008-06-19

    申请号：US11610841

    申请日：2006-12-14

    Applicant: Vinodh Gopal ,  Wajdi Feghali ,  Gilbert Wolrich ,  Daniel Cutter ,  Robert P. Ottavi

    Inventor： Vinodh Gopal ,  Wajdi Feghali ,  Gilbert Wolrich ,  Daniel Cutter ,  Robert P. Ottavi

    IPC: G06F7/38

    CPC classification number: G06F7/723

    Abstract: The present disclosure provides a system and method for performing modular exponentiation. The method includes loading a first word of a vector from memory into a first register and subsequently loading the first word from the first register to a second register. The method may also include loading a second word into the first register and loading at least one bit from the second register into an arithmetic logic unit. The method may further include performing modular exponentiation on the at least one bit to generate a result and generating a public key based upon, at least in part, the result. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

    Abstract translation: 本公开提供了一种用于执行模幂运算的系统和方法。 该方法包括将来自存储器的向量的第一字加载到第一寄存器中，并随后将第一个字从第一寄存器加载到第二寄存器。 该方法还可以包括将第二字加载到第一寄存器中并将至少一个比特从第二寄存器加载到算术逻辑单元中。 该方法还可以包括在至少一个比特上执行模幂运算以产生结果，并且至少部分地基于结果生成公开密钥。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

    Read lock miss control and queue management
    19.
    发明授权
    Read lock miss control and queue management 有权
    读锁定错误控制和队列管理

    公开(公告)号：US06681300B2

    公开(公告)日：2004-01-20

    申请号：US09969436

    申请日：2001-10-02

    Applicant: Gilbert Wolrich ,  Daniel Cutter ,  William Wheeler ,  Matthew J. Adiletta ,  Debra Bernstein

    Inventor： Gilbert Wolrich ,  Daniel Cutter ,  William Wheeler ,  Matthew J. Adiletta ,  Debra Bernstein

    IPC: G06F1200

    CPC classification number: G06F9/52

    Abstract: Managing memory access to random access memory includes fetching a read lock memory reference request and placing the read lock memory reference request at the end of a read lock miss queue if the read lock memory reference request is requesting access to an unlocked memory location and the read lock miss queue contains at least one read lock memory reference request.

    Abstract translation: 管理对随机存取存储器的存储器访问包括获取读取锁定存储器引用请求并将读取的锁定存储器引用请求放置在读取锁定未命中队列的结尾，如果读取锁定存储器引用请求访问未锁定的存储器位置并读取 锁定未命中队列至少包含一个读锁定存储器引用请求。

    METHOD AND APPARATUS FOR A DICTIONARY COMPRESSION ACCELERATOR
    20.
    发明申请
    METHOD AND APPARATUS FOR A DICTIONARY COMPRESSION ACCELERATOR 有权

    公开(公告)号：US20220308763A1

    公开(公告)日：2022-09-29

    申请号：US17214470

    申请日：2021-03-26

    Applicant: James GUILFORD ,  Vinodh GOPAL ,  Daniel CUTTER

    Inventor： James GUILFORD ,  Vinodh GOPAL ,  Daniel CUTTER

    IPC: G06F3/06 ,  H03M7/30 ,  H03M7/40

    Abstract: Apparatus and method for dictionary accelerator compression. For example, one embodiment of an apparatus comprises: a plurality of cores; a compression/decompression accelerator coupled to or integral to one or more of the plurality of cores, the compression/decompression accelerator to perform decompression and compression operations in response to read and write operations, respectively, wherein responsive to notification of a compression job to compress a memory page or a portion thereof, a history buffer associated with the compression/decompression accelerator to is to be initialized with pre-configured dictionary data, the compression/decompression accelerator to match portions of the pre-configured dictionary data with portions of the memory page to generate compressed output data.

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