公开(公告)号：US20100268872A1

公开(公告)日：2010-10-21

申请号：US12762625

申请日：2010-04-19

Applicant: Dong Jin LEE ,  Taek-Sung KIM ,  Kwang Ho KIM ,  Seong Sik HWANG ,  Hyuck-Sun KWON

Inventor： Dong Jin LEE ,  Taek-Sung KIM ,  Kwang Ho KIM ,  Seong Sik HWANG ,  Hyuck-Sun KWON

IPC: G06F12/00 ,  G06F12/02

CPC classification number: G06F13/4234 ,  G06F12/0246 ,  G06F13/385 ,  G06F2212/7205 ,  G11C16/10

Abstract: A data storage system comprising a storage device comprising at least one nonvolatile memory, and a controller connected to the storage device through a channel. The memory controller sends part or all of a command, address and data for a next operation to the nonvolatile memory while the nonvolatile memory device is in a busy state. The memory controller then performs a background operation while the nonvolatile memory device remains in the busy state.

Abstract translation: 一种数据存储系统，包括包括至少一个非易失性存储器的存储设备和通过信道连接到存储设备的控制器。 存储器控制器在非易失性存储器件处于忙状态的同时，将用于下一操作的命令，地址和数据的一部分或全部发送到非易失性存储器。 然后，存储器控制器在非易失性存储器件保持在忙状态的同时执行后台操作。

公开(公告)号：US20100099448A1

公开(公告)日：2010-04-22

申请号：US12578651

申请日：2009-10-14

Applicant: Seung Won YIM ,  Dong Jin LEE ,  Dong Hwan CHOI ,  Hye Joon YI

Inventor： Seung Won YIM ,  Dong Jin LEE ,  Dong Hwan CHOI ,  Hye Joon YI

IPC: H04M1/00 ,  G09G5/00 ,  H04W4/00

CPC classification number: H04M1/72552 ,  H04M1/274516 ,  H04W4/12

Abstract: A method and apparatus for a portable terminal intuitively and easily inputs receiver information of a text message for use when the portable terminal transmits the text message to others or replies to the text message. The receiver information inputting method includes extracting and displaying a preset number of items, in response to a request to input receiver information; calling receiver information linked to an item that is selected from among the items; and inputting the called receiver information in a receiver information input field.

Abstract translation: 便携式终端的方法和装置在便携式终端向其他人发送文本消息或对文本消息的回复时直观且容易地输入文本消息的接收者信息以供使用。 接收机信息输入方法包括响应于输入接收机信息的请求提取和显示预设数量的项目; 呼叫与从所述项目中选择的项目相关联的接收者信息; 并将被叫接收机信息输入到接收机信息输入区域中。

公开(公告)号：US07586415B2

公开(公告)日：2009-09-08

申请号：US11553329

申请日：2006-10-26

Applicant: Dong-Jin Lee

Inventor： Dong-Jin Lee

IPC: G08B13/14

CPC classification number: G06K19/07749 ,  H01Q1/2225 ,  H01Q9/0407

Abstract: A radio frequency identification (RFID) tag is provided including a lower antenna, an upper antenna, a RFID chip, and a spacer. The lower antenna has a coupling projection at one end. The upper antenna has a coupling groove at one end. The RFID chip contains information of an object which can be communicated with a reader device. One end of the RFID chip is coupled with the projection of the lower antenna and the other end is coupled with the groove of the upper antenna. The spacer is between the antennas to isolate the antennas electrically. The antennas are combined on both sides of the spacer in parallel. The RFID chip is connected with the antennas and fitted on a top side or a bottom side of the spacer so that active signals are transmitted through the antennas to send the information in the RFID chip to the reader device.

Abstract translation: 提供了包括下天线，上天线，RFID芯片和间隔器的射频识别（RFID）标签。 下天线在一端具有耦合突起。 上天线在一端具有耦合槽。 RFID芯片包含可与读取器设备通信的对象的信息。 RFID芯片的一端与下部天线的突起连接，另一端与上部天线的凹槽连接。 间隔物在天线之间，以电隔离天线。 天线在间隔物的两侧并联组合。 RFID芯片与天线连接并且安装在间隔物的顶侧或底侧，使得有源信号通过天线传输，以将RFID芯片中的信息发送到读取器设备。

公开(公告)号：US07477715B2

公开(公告)日：2009-01-13

申请号：US11623925

申请日：2007-01-17

Applicant: Young-Yong Byun ,  Dong-Jin Lee ,  Hi-Choon Lee

Inventor： Young-Yong Byun ,  Dong-Jin Lee ,  Hi-Choon Lee

IPC: H03D3/24

CPC classification number: H03L7/0814 ,  H03K5/13 ,  H03K2005/00052

Abstract: A delay-locked loop (DLL) circuit includes a standby signal generating circuit, a front stage circuit, and a back stage circuit. The standby signal generating circuit generates a first standby signal and a second standby signal in response to an active signal, a crock enable signal, a first column address strobe (CAS) latency signal, and a second CAS latency signal. The front stage circuit compares the phase of an external clock signal and the phase of a feedback signal and delays the external clock signal based on the phase difference between the external clock signal and the feedback signal to generate a first clock signal. The back stage circuit executes interpolation and duty-cycle correction on the first clock signal.

Abstract translation: 延迟锁定环路（DLL）电路包括备用信号发生电路，前级电路和后级电路。 待机信号发生电路响应于有效信号，一个使能信号，一个第一列地址选通（CAS）等待时间信号和一个第二CAS等待时间信号，产生第一待机信号和第二备用信号。 前级电路将外部时钟信号的相位与反馈信号的相位进行比较，并且基于外部时钟信号和反馈信号之间的相位差来延迟外部时钟信号以产生第一时钟信号。 后级电路对第一时钟信号执行内插和占空比校正。

公开(公告)号：US20080285346A1

公开(公告)日：2008-11-20

申请号：US12219600

申请日：2008-07-24

Applicant: Yong-Joo Han ,  Dong-Jin Lee ,  Kwang-Chol Choe

Inventor： Yong-Joo Han ,  Dong-Jin Lee ,  Kwang-Chol Choe

IPC: G11C16/04 ,  G11C8/00

CPC classification number: G11C8/10

Abstract: A decoder, a memory system, and a physical position converting method thereof may detect whether an address count of an input address is equal to or greater than a predetermined value. A physical position of a semiconductor memory device corresponding to the input address may be converted if the address count is equal to or greater than the predetermined value.

Abstract translation: 解码器，存储器系统及其物理位置转换方法可以检测输入地址的地址计数是否等于或大于预定值。 如果地址计数等于或大于预定值，则可以转换对应于输入地址的半导体存储器件的物理位置。

公开(公告)号：US07444172B1

公开(公告)日：2008-10-28

申请号：US09457817

申请日：1999-12-09

Applicant: Dong-Jin Lee ,  Byung-Hun Hwang ,  Chul-Gyoo Park ,  Young-Seoung Joo

Inventor： Dong-Jin Lee ,  Byung-Hun Hwang ,  Chul-Gyoo Park ,  Young-Seoung Joo

IPC: H04Q7/20

CPC classification number: H04M1/6075 ,  H04M1/66

Abstract: A device and method for automatically controlling power of a radio mobile terminal connected to a hands-free kit and for preventing the radio mobile terminal from malfunctioning. In a power control method for automatically turning on a radio mobile terminal connected to a hands-free kit, the radio mobile terminal including a power control signal generator, a signal output terminal and a signal input terminal, the hands-free kit including a power-on signal generator and a signal detector, a power-on signal is supplied to the signal input terminal for a predetermined time period through the power-on signal generator when the radio mobile terminal is connected to the hands-free kit. After the predetermined time period elapses, generating the power-on signal is stopped. It is determined if the driving signal generated by the signal output terminal is detected through the signal detector. If the driving signal is detected, generating the power-on signal is stopped.

Abstract translation: 一种用于自动控制连接到免提套件的无线电移动终端的电力并防止无线电移动终端发生故障的装置和方法。 在一种用于自动接通连接到免提工具的无线电移动终端的功率控制方法中，所述无线移动终端包括功率控制信号发生器，信号输出端和信号输入端，所述免提组件包括功率 在信号发生器和信号检测器中，当无线电移动终端连接到免提套件时，通过电源接通信号发生器将电源接通信号提供给信号输入端口预定的时间段。 在经过预定时间段之后，停止产生通电信号。 确定通过信号检测器检测由信号输出端产生的驱动信号。 如果检测到驱动信号，则停止产生通电信号。

公开(公告)号：US20070200706A1

公开(公告)日：2007-08-30

申请号：US11553329

申请日：2006-10-26

Applicant: Dong-Jin Lee

Inventor： Dong-Jin Lee

IPC: G08B13/14

CPC classification number: G06K19/07749 ,  H01Q1/2225 ,  H01Q9/0407

Abstract: This invention relates to a radio frequency identification (RFID) tag and ceramic patch antenna for radio frequency identification systems. The radio frequency identification tag in accordance with this invention comprises; lower antenna member of which one end is formed with coupling projection for conjoining; upper antenna member of which one end is formed with coupling groove for conjoining; an RFID chip of which one end is conjoined with the coupling projection of the said lower antenna member and the other end is conjoined with the coupling groove of the said upper antenna member, containing the information of the objective management item which communicates with the terminal device; and a spacer which electrically isolates the said antenna members. The said antenna members are conjoined on the top and bottom sides of the said spacer in parallel direction. The RFID chip which is conjoined with the said antenna members is placed on the top or bottom side of the said spacer.The ceramic patch antenna in accordance with this invention comprises; a dielectric ceramic member formed with ceramic substance of which the permittivity is 4.0˜210 and formed with a feeder hole punched at the center; conductive film formed on one side of the said dielectric ceramic member; an earth plate affixed on the other side of the said dielectric ceramic and formed with a punched feeder hole at the center; a feeder pin which is inserted in the feeder hole of the said dielectric ceramic and contacted with and feeds electricity to the said conductive film. The said feeder pin is inserted into the feeder hole of the said dielectric ceramic. The said conductive film covers the feeder hole formed in the said dielectric ceramic and electrically contacts with the feeder pin inserted into the feeder hole, The feeder hole of the said earth plate is formed larger than the feeder hole of the said dielectric ceramic, so that electrically isolated with the said feeder pin.

公开(公告)号：US20070176657A1

公开(公告)日：2007-08-02

申请号：US11623925

申请日：2007-01-17

Applicant: Young-Yong Byun ,  Dong-Jin Lee ,  Hi-Choon Lee

Inventor： Young-Yong Byun ,  Dong-Jin Lee ,  Hi-Choon Lee

IPC: H03L7/06

CPC classification number: H03L7/0814 ,  H03K5/13 ,  H03K2005/00052

Abstract: A delay-locked loop (DLL) circuit includes a standby signal generating circuit, a front stage circuit, and a back stage circuit. The standby signal generating circuit generates a first standby signal and a second standby signal in response to an active signal, a crock enable signal, a first column address strobe (CAS) latency signal, and a second CAS latency signal. The front stage circuit compares the phase of an external clock signal and the phase of a feedback signal and delays the external clock signal based on the phase difference between the external clock signal and the feedback signal to generate a first clock signal. The back stage circuit executes interpolation and duty-cycle correction on the first clock signal.

Abstract translation: 延迟锁定环路（DLL）电路包括备用信号发生电路，前级电路和后级电路。 待机信号发生电路响应于有效信号，一个使能信号，一个第一列地址选通（CAS）等待时间信号和一个第二CAS等待时间信号，产生第一待机信号和第二备用信号。 前级电路将外部时钟信号的相位与反馈信号的相位进行比较，并且基于外部时钟信号和反馈信号之间的相位差来延迟外部时钟信号以产生第一时钟信号。 后级电路对第一时钟信号执行内插和占空比校正。

公开(公告)号：US07239560B2

公开(公告)日：2007-07-03

申请号：US10749521

申请日：2004-01-02

Applicant: Dong-Jin Lee ,  Kye-Hyun Kyung ,  Chang-Sik Yoo

Inventor： Dong-Jin Lee ,  Kye-Hyun Kyung ,  Chang-Sik Yoo

IPC: G11C7/00

CPC classification number: G11C7/1057 ,  G11C7/1051 ,  G11C2207/105

Abstract: A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation.

公开(公告)号：US20060083079A1

公开(公告)日：2006-04-20

申请号：US11252535

申请日：2005-10-18

Applicant: Sang-Joon Hwang ,  Dong-Jin Lee ,  Jung-Bae Lee

Inventor： Sang-Joon Hwang ,  Dong-Jin Lee ,  Jung-Bae Lee

IPC: G11C16/04

CPC classification number: G11C7/1051 ,  G11C5/147 ,  G11C7/1048 ,  G11C7/1057

Abstract: A data output buffer includes an output terminal, a buffer and a pull-down driver. The output terminal is coupled to a first end of a transmission line, the transmission line being coupled to a pull-up termination resistor at a second end. The buffer pulls up the output terminal to a first power supply voltage and pulls down the output terminal to a second power supply voltage based on an output data signal. The pull-down driver pre-emphasizes an initial stage of a pull-down driving operation of the output terminal based on the output data.

Abstract translation: 数据输出缓冲器包括输出端子，缓冲器和下拉驱动器。 输出端耦合到传输线的第一端，传输线在第二端耦合到上拉终端电阻。 缓冲器将输出端上拉至第一电源电压，并根据输出数据信号将输出端拉低至第二电源电压。 下拉驱动器基于输出数据预先强调输出端子的下拉驱动操作的初始阶段。