公开(公告)号：US20240389467A1

公开(公告)日：2024-11-21

申请号：US18197147

申请日：2023-05-15

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Eng-Huat Toh ,  Soh Yun Siah ,  Young Seon You ,  Kazutaka Yamane ,  Vinayak Bharat Naik ,  Chan Tze Ho Simon

IPC: H10N50/80 ,  H10N50/01

Abstract: Structures including a magnetic-tunnel-junction device and methods of forming such structures. The structure comprises a magnetic-tunnel-junction device that includes a first electrode having a first sidewall, a second electrode having a second sidewall facing the first sidewall of the first electrode, a pinned layer adjacent to the first sidewall of the first electrode, a free layer adjacent to the second sidewall of the second electrode, and a tunnel barrier layer between the free layer and the pinned layer.

公开(公告)号：US20240381794A1

公开(公告)日：2024-11-14

申请号：US18195414

申请日：2023-05-10

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Xinshu Cai ,  Shyue Seng Tan

IPC: H01L29/94

Abstract: Structures for a non-volatile programmable device and methods of forming a structure for a non-volatile programmable device. The structure comprises a first electrode including a corner and a sidewall that extends to the corner, a first dielectric layer adjacent to the first sidewall, a second dielectric layer adjacent to the first dielectric layer, and a second electrode including a portion inside a recess between the first dielectric layer and the second dielectric layer. The portion of the second electrode is disposed adjacent to the corner of the first electrode.

公开(公告)号：US12136649B2

公开(公告)日：2024-11-05

申请号：US17723665

申请日：2022-04-19

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Jianbo Zhou ,  Shiang Yang Ong ,  Namchil Mun ,  Hung Chang Liao ,  Zhongxiu Yang

IPC: H01L29/00 ,  H01L21/762 ,  H01L29/06

Abstract: Semiconductor structures including a deep trench isolation structure and methods of forming a semiconductor structure including a deep trench isolation structure. The semiconductor structure includes a semiconductor substrate having a device region, and a deep trench isolation structure in the semiconductor substrate. The deep trench isolation structure further includes a first portion, a second portion adjacent to the first portion, and a conductor layer in the first portion and the second portion. The conductor layer in the first portion of the deep trench isolation structure surrounds the device region. The conductor layer in the second portion of the deep trench isolation structure defines an electrical connection to the semiconductor substrate.

公开(公告)号：US20240365566A1

公开(公告)日：2024-10-31

申请号：US18140677

申请日：2023-04-28

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Kai Kang ,  Curtis Chun-I Hsieh ,  Jianxun Sun ,  Juan Boon Tan

IPC: H10B63/00

CPC classification number: H10B63/80

Abstract: Structures for a resistive random-access memory element and methods of forming a structure for a resistive random-access memory element. The structure comprises an interlayer dielectric layer including a first trench having a sidewall and a second trench having a sidewall adjacent to the sidewall of the first trench. The structure further comprises a first layer on the sidewall of the first trench, a second layer inside the second trench, and a third layer on the sidewall of the second trench. The first layer comprises a first metal, the second layer comprises a second metal, and the third layer comprises a dielectric material. The third layer includes a portion positioned between the first layer and the second layer.

公开(公告)号：US12101944B2

公开(公告)日：2024-09-24

申请号：US17172085

申请日：2021-02-10

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Desmond Jia Jun Loy ,  Eng Huat Toh ,  Shyue Seng Tan

IPC: H01L45/00 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/82 ,  H10N70/021 ,  H10N70/24 ,  H10N70/823 ,  H10N70/841 ,  H10N70/8833

Abstract: The embodiments herein relate to semiconductor memory devices and methods of forming the same. A semiconductor memory device is provided. The semiconductor memory device includes a memory cell having a first electrode, a second electrode, a switching layer, and a via structure. The second electrode is adjacent to a side of the first electrode and the switching layer overlays uppermost surfaces of the first and second electrodes. The via structure is over the uppermost surface of the second electrode.

公开(公告)号：US20240297238A1

公开(公告)日：2024-09-05

申请号：US18177251

申请日：2023-03-02

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Abhijit Ghosh ,  Suk Hee Jang ,  Deepthi Kandasamy ,  Young Seon You ,  Yoke Leng Lim

IPC: H01L29/66 ,  H01L21/8234 ,  H01L23/528

CPC classification number: H01L29/6656 ,  H01L21/823468 ,  H01L23/5283

Abstract: A structure includes a first metal structure including a first upper metal feature having a first sidewall spacer thereabout, and a first lower metal feature under the first upper metal feature. The first lower metal feature includes a sidewall devoid of the first sidewall spacer. The structure also includes a second metal structure spaced from the first metal structure. The second metal structure includes a second upper metal feature having a second sidewall spacer thereabout, and a second lower metal feature under the first upper metal feature. The second lower metal feature includes a sidewall devoid of the second sidewall spacer. A dielectric is between the first metal structure and the second metal structure. The dielectric is devoid of any voids therein, and the opening it fills has a high aspect ratio. A related method is also provided.

公开(公告)号：US20240234498A9

公开(公告)日：2024-07-11

申请号：US17969768

申请日：2022-10-20

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Xinshu Cai ,  Shyue Seng Tan ,  Vibhor Jain ,  John J. Pekarik

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L29/0847 ,  H01L29/7825

Abstract: Structures for a junction field-effect transistor and methods of forming a structure for a junction field-effect transistor. The structure comprises a first gate on a top surface of a semiconductor substrate, a second gate beneath the top surface of the semiconductor substrate, and a channel region in the semiconductor substrate. The first gate is positioned between a source and a drain, and the channel region positioned between the first gate and the second gate.

公开(公告)号：US12034039B2

公开(公告)日：2024-07-09

申请号：US17451172

申请日：2021-10-18

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： EeJan Khor ,  Ramasamy Chockalingam ,  Juan Boon Tan

IPC: H01L49/02

CPC classification number: H01L28/92

Abstract: A capacitor structure for an integrated circuit (IC) and a related method of forming are disclosed. The capacitor structure includes three electrodes. A planar bottom electrode has a first insulator layer thereover. A middle electrode includes a conductive layer over the first insulator layer and a plurality of spaced conductive pillars contacting the conductive layer. A second insulator layer extends over and between the plurality of spaced conductive pillars and contacts the conductive layer. An upper electrode extends over the second insulator layer, and hence, over and between the plurality of spaced conductive pillars. A length of the upper electrode can be controlled, in part, by the number and dimensions of the conductive pillars to increase capacitance capabilities per area.

公开(公告)号：US20240194714A1

公开(公告)日：2024-06-13

申请号：US18064890

申请日：2022-12-12

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Ping ZHENG ,  Eng Huat TOH ,  Cancan WU ,  Kiok Boone Elgin QUEK

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/1462 ,  H01L27/14627 ,  H01L27/14683

Abstract: A photodiode device includes a semiconductor substrate, a plurality of pixels, each of the pixels including a diode structure on a first side of the substrate and a conductive layer on a second side of the substrate, and DTI structures isolating adjacent pixels from one another, the DTI structures including a conductive material that electrically couples the conductive layer on the second side of the substrate and a metal line on the first side of the substrate. The conductive material in the DTI structures is part of an electrode circuit for the pixels.

公开(公告)号：US20240194667A1

公开(公告)日：2024-06-13

申请号：US18077299

申请日：2022-12-08

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Kyongjin Hwang ,  Robert Gauthier, JR.

IPC: H01L27/02

CPC classification number: H01L27/0259

Abstract: Structures for an electrostatic discharge protection device and methods of forming same. The structure comprises a semiconductor substrate including first and second trench isolation regions positioned in the semiconductor substrate. The first trench isolation region extends to a first depth in the semiconductor substrate, and the second trench isolation region extends to a second depth in the semiconductor substrate. The second depth is greater than the first depth. A bipolar junction transistor structure includes a collector, an emitter, and a base each disposed in the semiconductor substrate. The collector includes a portion that extends to the top surface of the semiconductor substrate, the first trench isolation region is positioned in the base, the second trench isolation region is positioned in a lateral direction between the portion of the collector and the base, and the second trench isolation region surrounds the base, the emitter, and the first trench isolation region.