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公开(公告)号：US20220171001A1
公开(公告)日：2022-06-02
申请号：US17105675
申请日：2020-11-27
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor： Ping ZHENG , Eng Huat TOH , Yongshun SUN
Abstract: A magnetic field sensor may include a semiconductor structure having a planar surface, and first, second, and third sensing devices. The semiconductor structure may include a semiconductor member having a two-dimensional electron gas therein, and an insulator member disposed on the semiconductor member. The first sensing device may be configured to sense magnetic field along a first axis parallel to the planar surface. The second sensing device may be configured to sense magnetic field along a second axis parallel to the planar surface, and orthogonal to the first axis. The third sensing device may be configured to sense a magnetic field along a third axis normal to the planar surface. Each of the first, second, and third sensing devices may be formed in the semiconductor structure and may include electrodes that extend from the insulator member to the two-dimensional electron gas.
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公开(公告)号：US20210286025A1
公开(公告)日：2021-09-16
申请号：US16817623
申请日：2020-03-13
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor： Yongshun SUN , Eng Huat TOH , Ping ZHENG
Abstract: A Hall effect sensor device may be provided, including one or more sensor structures. Each sensor structure may include: a base layer having a first conductivity type; a Hall plate region having a second conductivity type opposite from the first conductivity type arranged above the base layer; a first isolating region arranged around and adjoining the Hall plate region, and contacting the base layer; a plurality of second isolating regions arranged within the Hall plate region; and a plurality of terminal regions arranged within the Hall plate region. The first and second isolating regions may include electrically insulating material, and each neighboring pair of terminal regions may be electrically isolated from each other by one of the second isolating regions.
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公开(公告)号：US20210247470A1
公开(公告)日：2021-08-12
申请号：US16787226
申请日：2020-02-11
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor： Ping ZHENG , Eng Huat TOH , Kazutaka YAMANE , Shyue Seng TAN , Kiok Boone Elgin QUEK
Abstract: A semiconductor device may be provided including a first series portion and a second series portion electrically connected in parallel with the first series portion. The first series portion may include a first MTJ stack and a first resistive element electrically connected in series. The second series portion may include a second MTJ stack and a second resistive element electrically connected in series. The first resistive element may include a third MTJ stack and the second resistive element may include a fourth MTJ stack. The first, second, third, and fourth MTJ stacks may include a same number of layers, which may include a fixed layer, a free layer, and a tunnelling barrier layer between the fixed layer and the free layer. Alternatively, the first resistive element may include a first transistor and the second resistive element may include a second transistor.
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公开(公告)号：US20170345830A1
公开(公告)日：2017-11-30
申请号：US15674558
申请日：2017-08-11
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor： Ping ZHENG , Eng Huat TOH , Kiok Boone Elgin QUEK , Yuan SUN
IPC: H01L27/112 , H01L29/06 , H01L29/786 , H01L29/66 , H01L29/423 , B82Y40/00 , B82Y10/00
CPC classification number: H01L27/11206 , B82Y10/00 , B82Y40/00 , H01L23/5252 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/7851 , H01L29/7853 , Y10S977/765 , Y10S977/888 , Y10S977/943
Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate prepared with at least a first region for accommodating an anti-fuse based memory cell. A fin structure is formed in the first region. The fin structure includes top and bottom fin portions and includes channel and non-channel regions defined along the length of the fin structure. An isolation layer is formed on the substrate. The isolation layer has a top isolation surface disposed below a top fin surface, leaving the top fin portion exposed. At least a portion of the exposed top fin portion in the channel region is processed to form a sharpened tip profile at top of the fin. A gate having a gate dielectric and a metal gate electrode is formed over the substrate. The gate wraps around the channel region of the fin structure.
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公开(公告)号：US20150129975A1
公开(公告)日：2015-05-14
申请号：US14078554
申请日：2013-11-13
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor： Ping ZHENG , Eng Huat TOH , Elgin Kiok Boone QUEK
IPC: H01L27/115 , H01L49/02
CPC classification number: G11C17/14 , H01L27/11206 , H01L45/04 , H01L45/1206 , H01L45/146 , H01L45/165 , H01L45/1675
Abstract: Devices and methods for forming a device are presented. The device includes a substrate having a device region and first and second isolation regions surrounding the device region. The device includes a multi-time programmable (MTP) memory cell having a single transistor disposed on the device region. The transistor includes a gate having a gate electrode over a gate dielectric which includes a programmable resistive layer. The gate dielectric is disposed over a channel region having first and second sub-regions in the substrate. The gate dielectric disposed above the first and second sub-regions has different characteristics such that when the memory cell is programmed, a portion of the programmable resistive layer above one of the first or second sub-region is more susceptible for programming relative to portion of the programmable resistive above the other first or second sub-region.
Abstract translation: 提出了用于形成装置的装置和方法。 该器件包括具有器件区域的衬底和围绕器件区域的第一和第二隔离区域。 该器件包括具有设置在器件区域上的单个晶体管的多时间可编程（MTP）存储单元。 该晶体管包括栅极，该栅极在栅极电介质上方具有包括可编程电阻层的栅电极。 栅极电介质设置在衬底中具有第一和第二子区域的沟道区域上。 布置在第一和第二子区域上方的栅极电介质具有不同的特性，使得当存储单元被编程时，在第一或第二子区域之一之上的可编程电阻层的一部分对于相对于 在另一个第一或第二子区域之上的可编程电阻。
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Patent Agency Ranking
公开(公告)号：US20240194714A1
公开(公告)日：2024-06-13
申请号：US18064890
申请日：2022-12-12
Applicant: GlobalFoundries Singapore Pte. Ltd.
Inventor： Ping ZHENG , Eng Huat TOH , Cancan WU , Kiok Boone Elgin QUEK
IPC: H01L27/146
CPC classification number: H01L27/1463 , H01L27/1462 , H01L27/14627 , H01L27/14683
Abstract: A photodiode device includes a semiconductor substrate, a plurality of pixels, each of the pixels including a diode structure on a first side of the substrate and a conductive layer on a second side of the substrate, and DTI structures isolating adjacent pixels from one another, the DTI structures including a conductive material that electrically couples the conductive layer on the second side of the substrate and a metal line on the first side of the substrate. The conductive material in the DTI structures is part of an electrode circuit for the pixels.
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公开(公告)号：US20250072149A1
公开(公告)日：2025-02-27
申请号：US18455320
申请日：2023-08-24
Applicant: GlobalFoundries Singapore Pte. Ltd.
Inventor： Ping ZHENG , Eng Huat TOH , Kiok Boone Elgin QUEK , Cancan Wu
IPC: H01L27/146
Abstract: A photodiode device includes a layer of semiconductor material, a plurality of pixels, each of the pixels including a diode structure on a first side of the layer of semiconductor material and a conductive layer on a second side of the layer of semiconductor material, deep trench isolation (DTI) structures isolating adjacent pixels from one another, a first vertical conductive layer over a first side of each DTI structure, and a second vertical conductive layer over a second side of each DTI structure. The first vertical conductive layer extends from the conductive layer to a first contact on the first side of each DTI structure, and the second vertical conductive layer extends from the conductive layer to a second contact on the second side of each DTI structure.
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公开(公告)号：US20220107372A1
公开(公告)日：2022-04-07
申请号：US17063099
申请日：2020-10-05
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor： Yongshun SUN , Eng Huat TOH , Ping ZHENG
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to 3-contact hall sensors and methods of manufacture and modes of operation. The structure includes: a plurality of sensing blocks each of which include a plurality of contacts; a first switching element connecting to a first set of sensing blocks of the plurality of sensing blocks; and a second switching element connecting to a second set of sensing blocks of the plurality of sensing blocks.
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公开(公告)号：US20180158817A1
公开(公告)日：2018-06-07
申请号：US15365965
申请日：2016-12-01
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor： Ping ZHENG , Eng Huat TOH
IPC: H01L27/088 , H01L21/8234 , H01L29/66 , H01L29/78
CPC classification number: H01L27/0886 , H01L21/823412 , H01L21/823431 , H01L21/823468 , H01L21/823481 , H01L29/4966 , H01L29/518 , H01L29/66545 , H01L29/7833 , H01L29/785
Abstract: Devices and methods for forming a device are disclosed. A substrate is provided. A plurality of fin structures are formed in the substrate. The fin structures include an upper part and a lower part. An isolation layer is formed on the substrate. The lower part of the plurality of fin structures is embedded in the isolation layer. A source including a first source portion and a second source portion is formed in a first side of the substrate. The first source portion partially occupies the fin structures along a length direction. The second source portion is formed over the first source portion. The second source portion elevates the fin structures. A drain is formed in a second side of the substrate. A distance between the source to the drain defines a channel region. A gate having a gate dielectric and a metal gate electrode is formed over the substrate. The gate wraps around the elevated fin structures and channel region.
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公开(公告)号：US20170358734A1
公开(公告)日：2017-12-14
申请号：US15176172
申请日：2016-06-08
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor： Ping ZHENG , Eng Huat TOH , Elgin Kiok Boone QUEK
CPC classification number: H01L43/02 , H01L27/228 , H01L43/08 , H01L43/10 , H01L43/12
Abstract: Devices and methods for forming a device are disclosed. A substrate having circuit component formed on a substrate surface is provided. Back end of line processing is performed to form an upper inter level dielectric (ILD) layer over the substrate. The upper ILD layer includes a plurality of ILD levels. A pair of magnetic tunneling junction (MTJ) stacks is formed in between adjacent ILD levels of the upper ILD layer. Each of the MTJ stack includes a fixed layer, a tunneling barrier layer and a free layer. The fixed layer has a first width. The tunneling barrier layer is formed on the fixed layer. The free layer is formed on the tunneling barrier layer. The free layer has a second width. The first width is wider than the second width.
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