公开(公告)号：US12204146B2

公开(公告)日：2025-01-21

申请号：US17869065

申请日：2022-07-20

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/125 ,  G02B6/122 ,  G02B6/136 ,  G02B6/12

Abstract: Structures for a waveguide crossing and methods of forming such structures. The structure comprises a first waveguide core including a first section, a second section, and a first longitudinal axis. The first section and the second section are aligned along the first longitudinal axis, the first section is terminated by a first end, the second section is terminated by a second end, and the first end of the first section is longitudinally spaced from the second end of the second section by a gap. The structure further comprises a second waveguide core having a second longitudinal axis angled relative to the first longitudinal axis. The second longitudinal axis of the second waveguide core crosses the first longitudinal axis of the first waveguide core within the gap.

公开(公告)号：US20250023565A1

公开(公告)日：2025-01-16

申请号：US18350294

申请日：2023-07-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva Kumar Chinthu

IPC: H03K19/0185

Abstract: Disclosed structures include a single-stage and a multi-stage voltage level shifter. Each structure includes multiple transistors, which are optionally all symmetric low-voltage transistors, and the structures are configured to avoid operation outside the safe operating area (SOA) of such transistors. The single-stage voltage level shifter and the first stage of the multi-stage voltage level shifter can be essentially identical. In operation, input voltage pulses (including an input voltage pulse transitioning between a first positive voltage (V1) equal to the voltage rating of the transistors and ground) can be received at source nodes of N-type transistors and, in response, output voltage pulses (including an intermediate output voltage pulse transitioning between V1 and a second positive voltage (V2) that is higher than (e.g., double) V1 and an output voltage pulse that transitions between ground and V2) can be output.

公开(公告)号：US12199147B2

公开(公告)日：2025-01-14

申请号：US17734135

申请日：2022-05-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vvss Satyasuresh Choppalli ,  Anupam Dutta ,  Aaron Lee Vallett

IPC: H01L29/10 ,  H01L21/74

Abstract: The present disclosure relates to a semiconductor device including a substrate, a first region disposed in the substrate, a terminal region disposed in the first region, a body contact region disposed in the first region and spaced apart from the terminal region, a dielectric layer disposed on the substrate over the first region between the terminal region and the body contact region, an electrically conductive layer disposed on the dielectric layer, and a continuous metallic layer disposed on the electrically conductive layer and extending to the body contact region, the continuous metallic layer disposed on the body contact region and in physical contact with a top and side portions of the electrically conductive layer. The semiconductor device may additionally include a body contact interconnect disposed on a portion of the continuous metallic layer over the electrically conductive layer.

公开(公告)号：US12191361B2

公开(公告)日：2025-01-07

申请号：US17656277

申请日：2022-03-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ketankumar Harishbhai Tailor

IPC: H01L29/40 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H10B69/00

Abstract: A transistor structure with a multi-layer field plate and related methods are disclosed. The transistor structure includes a dielectric layer that has a thinner portion over a first doped well and a second doped well, and a thicker portion adjacent the thinner portion and over the second doped well. The thicker portion has a height greater than the thinner portion above the doped wells. The transistor includes a first gate structure on the thinner portion and a field plate on the thicker portion of the dielectric layer.

公开(公告)号：US12189183B2

公开(公告)日：2025-01-07

申请号：US18046189

申请日：2022-10-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Won Suk Lee ,  Andreas D. Stricker

IPC: G02B6/126 ,  G02B6/122 ,  G02B6/27 ,  G02B6/12 ,  G02B6/125

Abstract: A structure includes a polarization device such as a polarization splitter, a polarization combiner or a polarization splitter rotator including a waveguide having a light absorber at an end section with an at least hook shape, e.g., it can be hooked or spiral shape. The structure also includes another waveguide adjacent the stated waveguide. The hook or spiral shape acts as a light absorber that reduces undesired optical noise such as excessive light insertion loss and/or light scattering. The hook or spiral shape may also be used on supplemental waveguides used to further filter and/or refine an optical signal in one of the waveguides of the polarization device, e.g., downstream of an output section of the polarization splitter and/or rotator.

公开(公告)号：US20250006842A1

公开(公告)日：2025-01-02

申请号：US18345001

申请日：2023-06-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： George Robert Mulfinger ,  Selina A. Mala ,  Pushparaj Dirgharaj Pathak ,  Chung Foong Tan

IPC: H01L29/78 ,  H01L21/84 ,  H01L27/12

Abstract: A structure includes a substrate, a first transistor on the substrate and a second transistor on the substrate. The second transistor is spaced apart from the first transistor by an isolation region. At least one stress-inducing liner is over the first transistor and the second transistor. An opening extends through at least one stress-inducing liner over at least the isolation region, and a dielectric layer is in at least a portion of the opening. The structure allows for local enhanced high-pressure deuterium (HPD) passivation, which increases threshold voltage of the transistors and improves hot carrier injection with no additional masking. A method of forming the structure is also provided.

公开(公告)号：US12183394B2

公开(公告)日：2024-12-31

申请号：US18487202

申请日：2023-10-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vivek Raj ,  Shivraj Gurpadappa Dharne ,  Mahbub Rashed

IPC: G11C11/41 ,  G11C11/412 ,  G11C11/419 ,  H03K3/356

Abstract: Embodiments of the disclosure provide a circuit structure and related method to provide a radiation resistant memory cell. A circuit structure may include a first latch having an input node and an output node. A second latch has an input node and an output node, in which the output node of the second latch is coupled to the input node of the first latch, and the input node of the second latch is coupled to the output node of the first latch. A read/write (R/W) circuit includes a plurality of transistors coupling a word line, a bit line, and an inverted bit line to at least two outputs. One of the at least two outputs is coupled to the input node of the first latch and another of the outputs is coupled to the input node of the second latch.

公开(公告)号：US20240429128A1

公开(公告)日：2024-12-26

申请号：US18340220

申请日：2023-06-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anupam Dutta ,  Satyasuresh VVss Choppalli ,  Rui Tze Toh

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H01L29/78

Abstract: Disclosed structures and methods include a top chip flipped relative to a bottom chip and bonded thereto. On the top chip, dielectric material layers separate a transistor from the bottom chip. The transistor includes source and drain regions; a body region on a channel region between the source and drain regions; and a gate structure adjacent to and between the channel region and the dielectric material layers. Alternatively, the transistor includes: a source region between drain regions; a body region on a channel region between the source region and each drain region; and gate structures adjacent to and between the channel regions and the dielectric material layers. The first chip also includes an insulator layer on the transistor opposite the dielectric material layers, a trench in the insulator layer extending to the source and body regions, and a local interconnect at the bottom of the trench.

公开(公告)号：US20240429127A1

公开(公告)日：2024-12-26

申请号：US18340174

申请日：2023-06-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Dewei Xu ,  Ravi Prakash Srivastava ,  Zhuojie Wu

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532

Abstract: A structure includes a through semiconductor via (TSV) in a semiconductor substrate. The structure also includes a cavity including a first cavity portion in the semiconductor substrate and surrounding a middle section of the TSV and in direct contact with the TSV. The cavity also includes a plurality of second cavity portions in the semiconductor substrate and surrounding an upper section of the TSV. The semiconductor substrate is between adjacent second cavity portions, creating a bridge portion that provides structural support. The cavity reduces parasitic capacitance.

公开(公告)号：US20240427177A1

公开(公告)日：2024-12-26

申请号：US18212437

申请日：2023-06-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02F1/015 ,  G02F1/025 ,  G02F1/035

Abstract: Plasmonic photonic structures that include a layer that exhibits an electric-field-induced Pockels effect and methods of forming such structures. The structure comprises a waveguide core on a substrate, a first layer that has an overlapping relationship with the first waveguide core, and a second layer that has an overlapping relationship with the first waveguide core and the first layer. The first layer comprises a metal, and the second layer comprising a material that exhibits an electric-field-induced Pockels effect.