公开(公告)号：US07315472B2

公开(公告)日：2008-01-01

申请号：US11420367

申请日：2006-05-25

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: G11C16/02 ,  G11C8/12 ,  G11C8/14 ,  G11C5/06

CPC classification number: G11C16/0483 ,  G11C16/24

Abstract: A non-volatile memory device may include a plurality of memory blocks including memory cells connected in series to bit lines, respectively. Each of the plurality of memory blocks may include a first sub memory block having a first group of memory cells, which are respectively connected in series between first select transistors connected to the bit lines, respectively, and second select transistors connected to a common source line, and a second sub memory block having a second group of memory cells, which are respectively connected in series between third select transistors connected to the bit lines, respectively, and fourth select transistors connected to the common source line.

Abstract translation: 非易失性存储器件可以包括分别与位线串联连接的存储器单元的多个存储器块。 多个存储块中的每一个可以包括具有分别连接到位线的第一选择晶体管和连接到公共源极线的第二选择晶体管之间的第一组存储器单元的第一子存储器块 以及具有分别连接到位线的第三选择晶体管之间的第二组存储单元的第二子存储块以及连接到公共源极线的第四选择晶体管。

公开(公告)号：US06934193B2

公开(公告)日：2005-08-23

申请号：US10364137

申请日：2003-02-11

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: H01L21/8247 ,  G11C16/14 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04

CPC classification number: G11C11/14 ,  G11C16/14 ,  G11C16/16

Abstract: Methods are disclosed for erasing a flash memory cell including: (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain, (e) a well, the gate including: (1) a tunnel oxide film, (2) a floating gate, (3) a dielectric film and (4) a control gate stacked on the semiconductor substrate. In one of the disclosed methods, a positive bias voltage is applied to the control gate, the source and drain are floated, a negative bias voltage is applied to the well, a ground voltage is then applied to the well while maintaining the positive bias voltage at the control gate, and subsequently a ground voltage is applied to the control gate.

Abstract translation: 公开了一种用于擦除闪存单元的方法，包括：（a）半导体衬底，（b）栅极，（c）源极，（d）漏极（e）阱，所述栅极包括：（1） 隧道氧化膜，（2）浮栅，（3）电介质膜和（4）堆叠在半导体衬底上的控制栅。 在所公开的方法之一中，将正偏置电压施加到控制栅极，源极和漏极浮置，将负偏压施加到阱，然后将接地电压施加到阱，同时保持正偏置电压 在控制栅极处，然后将接地电压施加到控制栅极。

公开(公告)号：US06339006B1

公开(公告)日：2002-01-15

申请号：US09609337

申请日：2000-06-30

Applicant: Min Kyu Lee ,  Hee Hyun Chang ,  Hee Youl Lee ,  Dong Kee Lee

Inventor： Min Kyu Lee ,  Hee Hyun Chang ,  Hee Youl Lee ,  Dong Kee Lee

IPC: H01L21331

CPC classification number: H01L29/7887 ,  G11C11/5621 ,  G11C16/0458 ,  G11C2211/5612 ,  H01L21/28273

Abstract: The invention relates to a flash EEPROM cell and method of manufacturing the same. The method of manufacturing a flash EEPROM cell includes sequentially forming a tunnel oxide film, a polysilicon layer for a floating gate and a hard mask layer on a semiconductor substrate; patterning the hard mask layer and then forming a hard mask layer spacer at the etching side of the patterned hard mask layer; removing the exposed portion of the polysilicon layer for the floating gate by etching process using the patterned hard mask layer and the hard mask layer spacer as etching masks thus to form first and second patterns that are separated in two; removing the patterned hard mask layer and the hard mask layer spacer and then depositing a dielectric film and a polysilicon layer for a control gate on the entire structure, thus forming a first floating gate, a second floating gate and a control gate by self-aligned etching process; and forming a drain junction and a source junction by cell source/drain ion implantation process. Thus, the present invention can prevent lower of the quality of the tunnel oxide film and thus increase the coupling ratio.

Abstract translation: 本发明涉及一种快闪EEPROM单元及其制造方法。 制造快闪EEPROM单元的方法包括在半导体衬底上依次形成隧道氧化膜，浮栅的多晶硅层和硬掩模层; 图案化硬掩模层，然后在图案化硬掩模层的蚀刻侧形成硬掩模层间隔物; 通过使用图案化的硬掩模层和硬掩模层间隔物作为蚀刻掩模的蚀刻工艺去除用于浮置栅极的多晶硅层的暴露部分，从而形成两个分离的第一和第二图案; 去除图案化的硬掩模层和硬掩模层间隔物，然后在整个结构上沉积用于控制栅极的电介质膜和多晶硅层，从而通过自对准形成第一浮栅，第二浮栅和控制栅 蚀刻工艺; 以及通过电池源/漏离子注入工艺形成漏极结和源极结。 因此，本发明可以防止隧道氧化膜的质量降低，从而增加耦合比。

公开(公告)号：US6067249A

公开(公告)日：2000-05-23

申请号：US220594

申请日：1998-12-28

Applicant: Hee-Youl Lee ,  Jae-Hyun Sone

Inventor： Hee-Youl Lee ,  Jae-Hyun Sone

IPC: H01L21/8247 ,  G11C5/02 ,  G11C16/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C5/02 ,  G11C16/0416

Abstract: A layout of a flash memory and a formation method of the same are disclosed. The layout includes a plurality of memory cells each having a cell transistor having a cell gate electrode having a floating gate and a control gate, and a source/drain electrode for thereby storing and erasing a data, a selection transistor having two gate electrodes, a common drain electrode between the gate electrodes and a source electrode formed outside the same and having a predetermined channel width larger than two times compared to the channel width of the cell transistor, and the drain electrode and source electrodes which are crossingly formed to each other with respect to the axis of the word lines through which a driving voltage is applied to the gate electrodes for thereby selecting a corresponding memory cell, a pair of cell bit lines connected with the source electrode of the selection transistor and connected in parallel with the drain electrode of the memory cell transistor for inputting/outputting the data to the cell transistor, and a pair of array bit lines connected with a drain electrode of the selection transistor and a peripheral circuit.

Abstract translation: 公开了闪速存储器的布局及其形成方法。 该布局包括多个存储单元，每个存储单元具有一个单元晶体管，该单元晶体管具有一个具有浮置栅极和一个控制栅极的单元栅极电极，以及用于存储和擦除数据的源极/漏极电极，具有两个栅电极的选择晶体管， 栅电极之间的公共漏电极和形成在其外部的源电极，并且具有与单元晶体管的沟道宽度相比大于两倍的预定沟道宽度的漏极电极，以及与电池晶体管彼此交叉形成的漏电极和源电极， 相对于通过其向驱动电压施加到栅电极的字线的轴，从而选择相应的存储单元，与选择晶体管的源电极连接并与漏电极并联连接的一对单元位线 用于将数据输入/输出到单元晶体管的存储单元晶体管，以及一对阵列位线连接 与选择晶体管的漏电极和外围电路相连。

公开(公告)号：US5864501A

公开(公告)日：1999-01-26

申请号：US963980

申请日：1997-11-04

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: H01L21/66 ,  G11C16/06 ,  G11C29/04 ,  G11C29/12 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C29/00

CPC classification number: G11C29/04

Abstract: This invention relates to a test pattern structure comprising a test pattern structure for endurance test of a flash memory device comprising: at least three active regions formed on a semiconductor substrate, each active region being isolated by a field oxide film; a common drain region formed on each active region, respectively; source regions formed on left and right sides of the common drain region in each active region, respectively; a first common floating gate formed along left side of each common drain region; a second common floating gate formed along right side of each common drain region; a control gate overlapped with the first and second floating gates, respectively and connected from each other at both ends of the first and second floating gates; a select gate formed over the common drain region, the source regions and the control gate in each active region, respectively; and metal wires connected to the common drain region, the source regions and the control gate in each active region, respectively.

Abstract translation: 本发明涉及一种测试图案结构，其包括用于闪速存储器件的耐久性测试的测试图案结构，包括：形成在半导体衬底上的至少三个有源区域，每个有源区域由场氧化膜隔离; 分别形成在每个有源区上的公共漏极区; 源区域分别形成在每个有源区域中的公共漏极区域的左侧和右侧; 沿着每个公共漏极区域的左侧形成的第一公共浮动栅极; 沿着每个公共漏极区域的右侧形成的第二公共浮动栅极; 分别与所述第一和第二浮动栅极重叠的控制栅极，并且在所述第一和第二浮动栅极的两端彼此连接; 分别在每个有源区域中的公共漏极区域，源极区域和控制栅极上形成的选择栅极; 以及金属线分别连接到每个有源区域中的公共漏极区域，源极区域和控制栅极。

公开(公告)号：US08422305B2

公开(公告)日：2013-04-16

申请号：US12826123

申请日：2010-06-29

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: G11C16/06

CPC classification number: G11C16/3404 ,  G11C16/0408

Abstract: A method of programming a nonvolatile memory device includes inputting program data to page buffers; performing a program operation and a program verification operation until threshold voltages of memory cells included in a selected page reach a target level according to the program data; when the threshold voltages of the memory cells reach the target level, performing an over-program verification operation to determine over-programmed memory cells in the memory cells; and making a determination of whether error checking and correction (ECC) processing for the over-programmed memory cells is feasible.

Abstract translation: 非易失性存储装置的编程方法包括将程序数据输入到页缓冲器; 执行程序操作和程序验证操作，直到所选页面中包括的存储器单元的阈值电压根据程序数据达到目标电平; 当存储器单元的阈值电压达到目标电平时，执行过程编程验证操作以确定存储器单元中的过程编程存储单元; 并且确定对于过度编程的存储器单元的错误校验和校正（ECC）处理是否可行。

公开(公告)号：US20120294091A1

公开(公告)日：2012-11-22

申请号：US13304569

申请日：2011-11-25

Applicant: Hee-Youl Lee

Inventor： Hee-Youl Lee

IPC: G11C16/34 ,  G11C16/26

CPC classification number: G11C16/0483 ,  G11C16/28 ,  G11C16/3404 ,  G11C16/3418

Abstract: A method for operating a non-volatile memory device which includes a plurality of memory cells serially coupled between a source selection transistor and a drain selection transistor, a first dummy memory cell coupled between the source selection transistor and the memory cells, and a second dummy memory cell coupled between the drain selection transistor and the memory cells includes applying a verification voltage to a gate of a selected memory cell, applying a first voltage to gates of unselected memory cells, and applying a second voltage that is lower than the first voltage to a gate of at least one of the first dummy memory cell and the second dummy memory cell, during a program verification operation.

Abstract translation: 一种用于操作非易失性存储器件的方法，该非易失性存储器件包括串联耦合在源极选择晶体管和漏极选择晶体管之间的多个存储器单元，耦合在源选择晶体管和存储单元之间的第一虚拟存储器单元，以及第二虚拟 耦合在漏极选择晶体管和存储单元之间的存储单元包括将验证电压施加到所选择的存储单元的栅极，向未选择的存储单元的栅极施加第一电压，以及将低于第一电压的第二电压施加到 在程序验证操作期间，所述第一伪存储单元和所述第二伪存储单元中的至少一个的门。

公开(公告)号：US08238153B2

公开(公告)日：2012-08-07

申请号：US12903968

申请日：2010-10-13

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427

Abstract: In a program method of a flash memory device where memory cells within a string are turned on to electrically connect channel regions, all of the channel regions within a second string are precharged uniformly by applying a ground voltage to a first bit line connected to a first string including to-be-programmed cells and a program-inhibited voltage to a second bit line connected to the second string including program-inhibited cells. If a program operation is executed, channel boosting occurs in the channel regions within the second string including the program-inhibited cells. Accordingly, a channel boosting potential can be increased and a program disturbance phenomenon, in which the threshold voltage of program-inhibited cells is changed, can be prevented.

Abstract translation: 在闪存器件的编程方法中，串联中的存储器单元导通以电连接沟道区，第二串中的所有沟道区均匀地通过将地电压施加到连接到第一栅极的第一位线 包括被编程单元的串和向连接到包括程序禁止单元的第二串的第二位线的程序禁止电压。 如果执行程序操作，则在包括程序禁止的单元的第二串内的通道区域中发生通道升压。 因此，可以增加通道增压电位，并且可以防止程序禁止的电池的阈值电压改变的程序干扰现象。

公开(公告)号：US20120170376A1

公开(公告)日：2012-07-05

申请号：US13339092

申请日：2011-12-28

Applicant: Hee Youl LEE ,  Keun Woo LEE

Inventor： Hee Youl LEE ,  Keun Woo LEE

IPC: G11C16/06

CPC classification number: G11C16/344 ,  G11C16/14 ,  G11C16/3418

Abstract: A semiconductor memory device includes a plurality of memory cells, including an N well formed within a P type region and a P well formed within the N well, a peripheral circuit configured to perform a program, program verify, read, erase, or erase verify operation on memory cells selected from among the memory cells, a voltage supply circuit configured to generate a positive voltage and a negative voltage for the program, program verify, read, erase, or erase verify operation, and a control circuit configured to control the peripheral circuit and the voltage supply circuit so that the program, program verify, read, erase, or erase verify operation is performed and, when the program verify and read operations are performed, different voltage is supplied to the P well and the N well.

Abstract translation: 半导体存储器件包括多个存储器单元，包括在P型区域内形成的N阱和形成在N阱内的P阱，配置为执行程序，程序验证，读取，擦除或擦除验证的外围电路 对从存储单元中选择的存储单元进行操作;电压供给电路，被配置为产生用于程序的正电压和负电压，程序验证，读取，擦除或擦除验证操作;以及控制电路， 电路和电压供应电路，以便执行程序，程序验证，读取，擦除或擦除验证操作，并且当执行程序验证和读取操作时，向P阱和N阱提供不同的电压。

公开(公告)号：US20120039127A1

公开(公告)日：2012-02-16

申请号：US13281312

申请日：2011-10-25

Applicant: Hee Youl LEE

Inventor： Hee Youl LEE

IPC: G11C16/08

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/3427

Abstract: A method for operating a flash memory device includes applying a pass voltage to a drain pass word line, a source pass word line, and unselected word lines. The drain pass word line is provided between a drain select line and a word line. The drain pass word line has a structure in the same manner as the word lines. The source pass word line is provided between a source select line and a word line. The source pass word line has a structure in the same manner as the word lines. A program voltage is applied to a selected word line associated with a selected memory cell block. A ground voltage is applied to drain pass word lines and source pass word lines. Word lines associated with unselected memory cell blocks are set to a floating state.

Abstract translation: 一种用于操作闪速存储器件的方法包括将通过电压施加到漏极通过字线，源极字线和未选字线。 漏极通行字线设置在漏极选择线和字线之间。 漏极字线具有与字线相同的结构。 在源选择线和字线之间提供源通过字线。 源通道字线具有与字线相同的结构。 将编程电压施加到与所选择的存储器单元块相关联的选定字线。 接地电压被施加到漏通字线和源通路字线。 与未选择的存储单元块相关联的字线设置为浮动状态。