公开(公告)号：US07300852B2

公开(公告)日：2007-11-27

申请号：US11089122

申请日：2005-03-24

Applicant: Ho Jin Cho ,  Jun Soo Chang ,  Eun A. Lee ,  Su Jin Chae ,  Young Dae Kim

Inventor： Ho Jin Cho ,  Jun Soo Chang ,  Eun A. Lee ,  Su Jin Chae ,  Young Dae Kim

IPC: H01L21/20

CPC classification number: H01L21/02312 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/3144 ,  H01L28/60

Abstract: A method for manufacturing a capacitor of a semiconductor element including: forming a bottom electrode of the capacitor on a semiconductor substrate; performing rapid thermal nitrification (RTN) on the upper surface of the bottom electrode; performing a thermal process on the obtained structure having the bottom electrode in a furnace under a nitride atmosphere to eliminate stress generated by the RTN; forming Al2O3 and HfO2 dielectric films on the nitrified bottom electrode; and forming a plate electrode of the capacitor on the Al2O3 and HfO2 dielectric films. The thermal process is performed after the RTN performed on the surface of the bottom electrode, so that stress, generated from the RTN, is alleviated, thereby allowing the capacitor to obtain a high capacitance and lowering leakage current.

Abstract translation: 一种制造半导体元件的电容器的方法，包括：在半导体衬底上形成电容器的底部电极; 在底电极的上表面进行快速热硝化（RTN）; 对所获得的在氮化物气氛下的炉中具有底部电极的结构进行热处理以消除由RTN产生的应力; 在硝化的底部电极上形成Al 2 O 3 N 3和HfO 2 N 2电介质膜; 以及在Al 2 O 3和HfO 2 N 2电介质膜上形成电容器的平板电极。 在底电极表面进行RTN之后进行热处理，从而可以减轻由RTN产生的应力，从而使电容器获得高电容，降低漏电流。

公开(公告)号：US06955974B2

公开(公告)日：2005-10-18

申请号：US10877714

申请日：2004-06-25

Applicant: Tae Hyeok Lee ,  Cheol Hwan Park ,  Dong Su Park ,  Ho Jin Cho ,  Eun A Lee

Inventor： Tae Hyeok Lee ,  Cheol Hwan Park ,  Dong Su Park ,  Ho Jin Cho ,  Eun A Lee

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/8242

CPC classification number: H01L21/76224 ,  H01L27/10894

Abstract: A method for forming an isolation layer of a semiconductor device, which comprises the steps of: a) sequentially forming a pad oxide layer and a pad nitride layer on a silicon substrate; b) etching the pad nitride layer, the pad oxide layer, and the silicon substrate, thereby forming a trench; c) thermal-oxidizing the resultant substrate to form a sidewall oxide layer on a surface of the trench; d) nitrifying the sidewall oxide layer through the use of NH3 annealing; e) depositing a liner aluminum nitride layer on an entire surface of the silicon substrate inclusive of the nitrated sidewall oxide layer; f) depositing a buried oxide layer on the liner aluminum nitride layer to fill the trench; g) performing a chemical mechanical polishing process with respect to the buried oxide layer; and h) eliminating the pad nitride layer.

Abstract translation: 一种用于形成半导体器件的隔离层的方法，包括以下步骤：a）在硅衬底上依次形成焊盘氧化物层和衬垫氮化物层; b）蚀刻衬垫氮化物层，衬垫氧化物层和硅衬底，从而形成沟槽; c）热氧化所得衬底以在沟槽的表面上形成侧壁氧化物层; d）通过使用NH 3退火对侧壁氧化物层进行硝化; e）在包括所述硝化侧壁氧化物层的所述硅衬底的整个表面上沉积衬里氮化铝层; f）在衬里氮化铝层上沉积掩埋氧化物层以填充沟槽; g）对所述掩埋氧化物层进行化学机械抛光工艺; 以及h）消除所述衬垫氮化物层。

公开(公告)号：US06685522B2

公开(公告)日：2004-02-03

申请号：US09877864

申请日：2001-06-08

Applicant: In Jung Yun ,  Ho Jin Cho ,  Bong Woo Lee ,  Byung Hoon Kang ,  Kwang Yun Choi

Inventor： In Jung Yun ,  Ho Jin Cho ,  Bong Woo Lee ,  Byung Hoon Kang ,  Kwang Yun Choi

IPC: H01J942

CPC classification number: H01J9/42 ,  H01J29/76

Abstract: Disclosed is a product quality test in a winding step of the entire manufacturing process of a deflection yoke, which is a core part of a display device employing a cathode ray tube such as a color TV or a monitor, and in particular, a winding zig for measuring magnetic fields of a deflection yoke and a magnetic field measuring system of a deflection yoke using the winding zig. The winding zig and the system according to the invention include a plurality of magnetic field sensors mounted inside of the A-shaped winding zig, a digital signal generator for receiving output signals from the magnetic field sensors that sense magnetic field characteristics of a deflection coil wound around the A-shaped winding zig, amplifying the received signals, and converting the amplified signals to digital signals, a digital signal interface for converting the data outputted from the digital signal generator to serial data, and a transmitter for receiving signals processed as serial data by the digital signal interface, and transmitting the received signals.

Abstract translation: 公开了作为使用诸如彩色电视或监视器的阴极射线管的显示装置的核心部分的偏转线圈的整个制造过程中的卷绕步骤中的产品质量测试，特别地，绕组Zig 用于测量偏转线圈的磁场和使用绕组曲线的偏转线圈的磁场测量系统。 根据本发明的绕组Zig和系统包括安装在A形绕组Zig内部的多个磁场传感器，一个数字信号发生器，用于接收来自磁场传感器的输出信号，该磁场传感器感测绕组的偏转线圈的磁场特性 围绕A形绕组Zig放大接收到的信号，并将放大的信号转换成数字信号，用于将从数字信号发生器输出的数据转换为串行数据的数字信号接口，以及用于接收作为串行数据处理的信号的发送器 通过数字信号接口，并发送接收到的信号。

公开(公告)号：US06437522B1

公开(公告)日：2002-08-20

申请号：US09865749

申请日：2001-05-25

Applicant: Bong Mo Moon ,  Ho Jin Cho ,  Ick Chan Shim

Inventor： Bong Mo Moon ,  Ho Jin Cho ,  Ick Chan Shim

IPC: H01J2951

CPC classification number: H04N17/04 ,  H04N5/68 ,  H04N9/28

Abstract: The invention and method enable the astigmatism correction at each crossing point of a cross hatch pattern, thereby making high-resolution display possible. An appropriate voltage or current for controlling the magnetic field adjusting coils are generated from the correction data stored in a memory. The voltage or current generated are then applied to two poles, four poles or six poles during scanning of the screen.

Abstract translation: 本发明和方法能够在交叉阴影图案的每个交叉点处进行像散校正，从而使得高分辨率显示成为可能。 从存储在存储器中的校正数据产生用于控制磁场调节线圈的适当电压或电流。 所产生的电压或电流在屏幕扫描期间被施加到两极，四极或六极。

公开(公告)号：US06319765B1

公开(公告)日：2001-11-20

申请号：US09473107

申请日：1999-12-28

Applicant: Ho Jin Cho ,  Kwon Hong

Inventor： Ho Jin Cho ,  Kwon Hong

IPC: H01L218242

CPC classification number: H01L28/55 ,  C23C16/18 ,  H01L28/60

Abstract: The present invention provides a method for fabricating a ferroelectric memory device to reduce manufacturing cost and to obtain the electric characteristic of capacitor. The method comprises the steps of: forming an intermetal insulating layer provided with a contact hole exposing a junction region formed on a semiconductor layer having the junction region; forming a contact plug within the contact hole; forming a barrier layer and a metal layer for lower electrode on the intermetal insulating layer successively; forming a lower electrode by patterning selected portions of the metal layer for lower electrode and the barrier layer; forming a high dielectric layer on the substrate on which the lower electrode is formed; and forming an upper electrode on the high dielectric layer, wherein during forming the upper electrode, an F ion layer to be trapped by dangling bonds formed at an interface between the upper electrode and the high dielectric layer, is formed at the interface.

Abstract translation: 本发明提供一种制造铁电存储器件的方法，以降低制造成本并获得电容器的电特性。该方法包括以下步骤：形成金属间绝缘层，该金属间绝缘层设有暴露半导体上形成的结区的接触孔 层具有接合区域; 在所述接触孔内形成接触塞; 在金属间绝缘层上形成用于下电极的阻挡层和金属层; 通过图案化用于下电极和阻挡层的金属层的选定部分来形成下电极; 在其上形成下电极的基板上形成高介电层; 以及在所述高电介质层上形成上电极，其中在形成所述上电极期间，在所述界面处形成要被形成在所述上电极和所述高电介质层之间的界面处的悬挂键捕获的F离子层。

公开(公告)号：US08470668B2

公开(公告)日：2013-06-25

申请号：US12979926

申请日：2010-12-28

Applicant: Ho Jin Cho ,  Cheol Hwan Park ,  Dong Kyun Lee

Inventor： Ho Jin Cho ,  Cheol Hwan Park ,  Dong Kyun Lee

IPC: H01L21/8242

CPC classification number: H01L27/10894 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/90

Abstract: An embodiment of the invention includes a pillar type capacitor where a pillar is formed over an upper portion of a storage node contact. A bottom electrode is formed over sidewalls of the pillar, and a dielectric film is formed over pillar and the bottom electrode. A top electrode is then formed over the upper portion of the dielectric film.

Abstract translation: 本发明的实施例包括柱形电容器，其中柱形成在存储节点接触件的上部上。 底部电极形成在支柱的侧壁上，电介质膜形成在支柱和底部电极之上。 然后在电介质膜的上部上形成顶部电极。

公开(公告)号：US07985645B2

公开(公告)日：2011-07-26

申请号：US12649610

申请日：2009-12-30

Applicant: Cheol Hwan Park ,  Ho Jin Cho ,  Dong Kyun Lee

Inventor： Cheol Hwan Park ,  Ho Jin Cho ,  Dong Kyun Lee

IPC: H01L21/8242

CPC classification number: H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10894

Abstract: A semiconductor device having a high aspect cylindrical capacitor and a method for fabricating the same is presented. The high aspect cylindrical type capacitor is a stable structure which is not prone to causing bunker defects and losses in a guard ring. The semiconductor device includes the cylindrical type capacitor structure, a storage node oxide, a guard ring hole, a conductive layer, and a capping oxide. The cylindrical type capacitor structure in a cell region includes a cylindrical type lower electrode, a dielectric and an upper electrode. The storage node oxide is in a peripheral region over the semiconductor substrate. The conductive layer coating the guard ring hole. The guard ring hole at a boundary of the peripheral region that adjoins the cell region over the semiconductor substrate. The capping oxide partially fills in a part of the conductive layer. The gapfill film filling in the rest of the conductive layer.

Abstract translation: 提出了具有高方位圆柱形电容器的半导体器件及其制造方法。 高档圆柱型电容器是一种稳定的结构，不容易造成保护环中的掩体缺陷和损失。 半导体器件包括圆柱形电容器结构，存储节点氧化物，保护环孔，导电层和封盖氧化物。 单元区域中的圆柱型电容器结构包括圆筒形下电极，电介质和上电极。 存储节点氧化物位于半导体衬底上的周边区域中。 导电层涂覆保护环孔。 在与半导体基板上的单元区域相邻的周边区域的边界处的保护环孔。 覆盖氧化物部分地填充导电层的一部分。 间隙填充膜填充在导电层的其余部分。

公开(公告)号：US20090269902A1

公开(公告)日：2009-10-29

申请号：US12499248

申请日：2009-07-08

Applicant: Ho Jin CHO ,  Cheol Hwan PARK ,  Jae Soo KIM ,  Dong Kyun LEE

Inventor： Ho Jin CHO ,  Cheol Hwan PARK ,  Jae Soo KIM ,  Dong Kyun LEE

IPC: H01L21/02

CPC classification number: H01L28/65 ,  H01L27/10852 ,  H01L28/91

Abstract: A capacitor is made by forming a buffer oxide layer, an etching stop layer, and a mold insulation layer over a semiconductor substrate having a storage node contact plug. The mold insulation layer and the etching stop layer are etched to form a hole in an upper portion of the storage node contact plug. A tapering layer is deposited over the mold insulation layer including the hole. The tapering layer and the buffer oxide layer are etched back so that the tapering layer is remained only at the upper end portion of the etched hole. A metal storage node layer formed on the etched hole over the remaining tapering layer. The mold insulation layer and the remaining tapering layer are removed to form a cylindrical storage node having a tapered upper end. A dielectric layer and a plate node are formed over the storage node.

Abstract translation: 通过在具有存储节点接触插塞的半导体衬底上形成缓冲氧化物层，蚀刻停止层和模具绝缘层来制造电容器。 蚀刻模具绝缘层和蚀刻停止层，以在存储节点接触插塞的上部形成孔。 在包括孔的模具绝缘层上沉积渐缩层。 锥形层和缓冲氧化物层被回蚀刻，使得锥形层仅保留在蚀刻孔的上端部。 在剩余的锥形层上形成在蚀刻孔上的金属储存节点层。 去除模具绝缘层和剩余的锥形层以形成具有锥形上端的圆柱形存储节点。 在存储节点上形成介电层和板状节点。

公开(公告)号：US20090206448A1

公开(公告)日：2009-08-20

申请号：US12244115

申请日：2008-10-02

Applicant: Ho Jin CHO ,  Cheol Hwan PARK ,  Jae Wook SEO ,  Jong Kuk KIM

Inventor： Ho Jin CHO ,  Cheol Hwan PARK ,  Jae Wook SEO ,  Jong Kuk KIM

IPC: H01L29/00 ,  H01L21/00

CPC classification number: H01L28/91 ,  H01L27/10852

Abstract: A semiconductor device that prevents the leaning of storage node when forming a capacitor having high capacitance includes a plurality of cylinder-shaped storage nodes formed over a semiconductor substrate; and support patterns formed to fix the storage nodes in the form of an ‘L’ or a ‘+’ when viewed from the top. This semiconductor device having support patterns in the form of an ‘L’ or a ‘+’ reduces stress on the storage nodes when subsequently forming a dielectric layer and plate nodes that prevents the capacitors from leaking.

Abstract translation: 当形成具有高电容的电容器时，防止存储节点倾斜的半导体器件包括形成在半导体衬底上的多个圆柱形存储节点; 以及当从顶部观察时，形成为以“L”或“+”的形式固定存储节点的支撑图案。 具有“L”或“+”形式的支撑图案的这种半导体器件随后形成介电层并且防止电容器泄漏的板节点减小了存储节点上的应力。

公开(公告)号：US06355521B1

公开(公告)日：2002-03-12

申请号：US09659509

申请日：2000-09-11

Applicant: Ho Jin Cho

Inventor： Ho Jin Cho

IPC: H01L21336

CPC classification number: H01L28/60 ,  H01L21/31604 ,  H01L28/91

Abstract: The present invention discloses a method of manufacturing a capacitor in a semiconductor device which is directed to solve the problem of reduction of capacitance occurring when manufacturing a capacitor of a MIS structure using poly-silicon as an underlying electrode and metal as an upper electrode in a capacitor using Ta2O5 as a dielectric film. In order to solve the problem, the present invention forms an underlying electrode using metal having a good oxide-resistant such as TiSiN. Thus, the present invention could not only lower the thickness of the effective oxide film of Ta2O5 when depositing Ta2O5 or performing a thermal process for crystallization but also prevent increase of a leak current due to oxidization of the underlying electrode and the diffusion prevention film, thus securing the capacitance of the capacitor and improving the electric characteristic of the capacitor.

Abstract translation: 本发明公开了一种在半导体器件中制造电容器的方法，该方法旨在解决当制造使用多晶硅作为底层电极的MIS结构的电容器和在金属作为上部电极的金属制造时发生的电容减小的问题 电容器采用Ta2O5作为电介质膜。 为了解决这个问题，本发明利用TiSiN等具有良好的耐氧化性的金属形成下层电极。 因此，本发明不仅可以降低Ta2O5的有效氧化膜的厚度，还可以防止由于底层电极和扩散防止膜的氧化引起的漏电流的增加， 确保电容器的电容并改善电容器的电气特性。