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    Phase change memory device and fabrication method thereof
    1.
    发明授权
    Phase change memory device and fabrication method thereof 有权
    相变存储器件及其制造方法

    公开(公告)号：US08609503B2

    公开(公告)日：2013-12-17

    申请号：US13357882

    申请日：2012-01-25

    Applicant: Keum Bum Lee ,  Su Jin Chae ,  Hye Jin Seo

    Inventor： Keum Bum Lee ,  Su Jin Chae ,  Hye Jin Seo

    IPC: H01L21/8239

    CPC classification number: H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

    Abstract: The manufacturing of a phase change memory device that includes a switching device, a bottom electrode contact in contact with the switching device and a porous spacer formed on the bottom electrode contact. The formed bottom electrode contact exposes a switching device on a semiconductor substrate which the switching device is formed in, forming an insulating layer on a resultant structure of the semiconductor substrate including the bottom electrode contact by using an insulating compound having materials with different atomic sizes, and forming an insulating spacer within the bottom electrode contact hole by selectively etching the insulating layer.

    Abstract translation: 一种相变存储器件的制造，其包括开关器件，与开关器件接触的底部电极触点和形成在底部电极触点上的多孔间隔物。 形成的底部电极接触使形成有开关器件的半导体衬底上的开关器件暴露，通过使用具有不同原子尺寸的材料的绝缘化合物，在包括底部电极接触的半导体衬底的合成结构上形成绝缘层， 以及通过选择性地蚀刻绝缘层，在底部电极接触孔内形成绝缘间隔物。

    Capacitor with nanotubes and method for fabricating the same
    3.
    发明申请
    Capacitor with nanotubes and method for fabricating the same 失效
    纳米管电容器及其制造方法

    公开(公告)号：US20090140385A1

    公开(公告)日：2009-06-04

    申请号：US12288880

    申请日：2008-10-24

    Applicant: Eun-A Lee ,  Ho-Jin Cho ,  Young-Dae Kim ,  Jun-Soo Chang ,  Su-Jin Chae ,  Hai-Won Kim

    Inventor： Eun-A Lee ,  Ho-Jin Cho ,  Young-Dae Kim ,  Jun-Soo Chang ,  Su-Jin Chae ,  Hai-Won Kim

    IPC: H01L29/00

    CPC classification number: B82Y10/00 ,  H01G4/005 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer. The method includes the steps of: forming a conductive layer for forming a lower electrode; forming a nanotube array including a plurality of nanotubes formed on the conductive layer without using a catalytic layer; forming a dielectric layer on the nanotube array; and forming an upper electrode on the dielectric layer.

    Abstract translation: 提供了一种具有纳米管的电容器及其制造方法。 所述电容器包括：下电极，其包括图案化导电层和形成在所述图案化导电层上的多个纳米管，所述多个纳米管不需要使用催化剂层; 形成在下电极上的电介质层; 以及形成在电介质层上的上电极。 该方法包括以下步骤：形成用于形成下电极的导电层; 在不使用催化剂层的情况下形成包括形成在所述导电层上的多个纳米管的纳米管阵列; 在纳米管阵列上形成介电层; 以及在所述电介质层上形成上电极。

    Method For Fabricating Semiconductor Device Having Metal Fuse
    4.
    发明申请
    Method For Fabricating Semiconductor Device Having Metal Fuse 审中-公开
    制造具有金属保险丝的半导体器件的方法

    公开(公告)号：US20080070398A1

    公开(公告)日：2008-03-20

    申请号：US11758512

    申请日：2007-06-05

    Applicant: Dong Su Park ,  Ho Jin Cho ,  Keum Bum Lee ,  Su Jin Chae ,  Cheol-Hwan Park

    Inventor： Dong Su Park ,  Ho Jin Cho ,  Keum Bum Lee ,  Su Jin Chae ,  Cheol-Hwan Park

    IPC: H01L23/525

    CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Disclosed herein is a method of fabricating a semiconductor device having a metal fuse. The method includes forming a plate electrode on a semiconductor substrate, forming an interlayer insulating layer on the plate electrode, forming a barrier metal layer containing either silicon or aluminum, a first metal layer and an antireflection layer containing either silicon or aluminum sequentially from bottom to top on the interlayer insulating layer. The method also includes patterning the antireflection layer, the first metal layer, and the barrier metal layer to form a first metal interconnection. The method also includes forming a fuse with the same material and structure as those of the first metal interconnection while forming the first metal interconnection. The method further includes forming an inter-metal dielectric layer on the first metal interconnection and the fuse, forming a second metal interconnection on the inter-metal dielectric layer, forming a passivation layer on the second metal interconnection, and forming a fuse box in the passivation layer.

    Abstract translation: 这里公开了一种制造具有金属保险丝的半导体器件的方法。 该方法包括在半导体衬底上形成平板电极，在平板电极上形成层间绝缘层，从底部依次形成含有硅或铝的阻挡金属层，第一金属层和含有硅或铝的抗反射层， 顶层在层间绝缘层上。 该方法还包括图案化抗反射层，第一金属层和阻挡金属层以形成第一金属互连。 该方法还包括形成具有与第一金属互连相同的材料和结构的熔丝，同时形成第一金属互连。 该方法还包括在第一金属互连和熔丝上形成金属间电介质层，在金属间绝缘层上形成第二金属互连，在第二金属互连上形成钝化层，并在第 钝化层。

    Method for manufacturing capacitor of semiconductor element
    5.
    发明授权
    Method for manufacturing capacitor of semiconductor element 失效
    制造半导体元件电容器的方法

    公开(公告)号：US07300852B2

    公开(公告)日：2007-11-27

    申请号：US11089122

    申请日：2005-03-24

    Applicant: Ho Jin Cho ,  Jun Soo Chang ,  Eun A. Lee ,  Su Jin Chae ,  Young Dae Kim

    Inventor： Ho Jin Cho ,  Jun Soo Chang ,  Eun A. Lee ,  Su Jin Chae ,  Young Dae Kim

    IPC: H01L21/20

    CPC classification number: H01L21/02312 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/3144 ,  H01L28/60

    Abstract: A method for manufacturing a capacitor of a semiconductor element including: forming a bottom electrode of the capacitor on a semiconductor substrate; performing rapid thermal nitrification (RTN) on the upper surface of the bottom electrode; performing a thermal process on the obtained structure having the bottom electrode in a furnace under a nitride atmosphere to eliminate stress generated by the RTN; forming Al2O3 and HfO2 dielectric films on the nitrified bottom electrode; and forming a plate electrode of the capacitor on the Al2O3 and HfO2 dielectric films. The thermal process is performed after the RTN performed on the surface of the bottom electrode, so that stress, generated from the RTN, is alleviated, thereby allowing the capacitor to obtain a high capacitance and lowering leakage current.

    Abstract translation: 一种制造半导体元件的电容器的方法，包括：在半导体衬底上形成电容器的底部电极; 在底电极的上表面进行快速热硝化（RTN）; 对所获得的在氮化物气氛下的炉中具有底部电极的结构进行热处理以消除由RTN产生的应力; 在硝化的底部电极上形成Al 2 O 3 N 3和HfO 2 N 2电介质膜; 以及在Al 2 O 3和HfO 2 N 2电介质膜上形成电容器的平板电极。 在底电极表面进行RTN之后进行热处理，从而可以减轻由RTN产生的应力，从而使电容器获得高电容，降低漏电流。

    Phase-change memory device and method for manufacturing the same
    8.
    发明授权
    Phase-change memory device and method for manufacturing the same 失效
    相变存储器件及其制造方法

    公开(公告)号：US07772101B2

    公开(公告)日：2010-08-10

    申请号：US12146184

    申请日：2008-06-25

    Applicant: Su-Jin Chae ,  Keum-Bum Lee ,  Min-Yong Lee

    Inventor： Su-Jin Chae ,  Keum-Bum Lee ,  Min-Yong Lee

    IPC: H01L21/44

    CPC classification number: H01L45/06 ,  H01L27/2409

    Abstract: A phase-change memory device and a fabrication method thereof, capable of reducing driving current while minimizing a size of a contact hole used for forming a PN diode in the phase-change memory device that employs the PN diode. The method of fabricating the phase-change memory device includes the steps of preparing a semiconductor substrate having a junction area formed with a dielectric layer, forming an interlayer dielectric layer having etching selectivity lower than that of the dielectric layer over an entire structure, and forming a contact hole by removing predetermined portions of the interlayer dielectric layer and the dielectric layer. The contact area between the PN diode and the semiconductor substrate is increased so that interfacial resistance is reduced.

    Abstract translation: 一种相变存储器件及其制造方法，其能够在使用PN二极管的相变存储器件中最小化用于形成PN二极管的接触孔的尺寸的同时降低驱动电流。 制造相变存储器件的方法包括以下步骤：制备具有形成有介电层的结区的半导体衬底，在整个结构上形成具有低于电介质层的蚀刻选择性的层间电介质层，以及形成 通过去除层间电介质层和电介质层的预定部分的接触孔。 PN二极管和半导体衬底之间的接触面积增加，从而降低界面电阻。

    Capacitor with nanotubes and method for fabricating the same
    9.
    发明授权
    Capacitor with nanotubes and method for fabricating the same 失效
    纳米管电容器及其制造方法

    公开(公告)号：US07463476B2

    公开(公告)日：2008-12-09

    申请号：US11148057

    申请日：2005-06-07

    Applicant: Eun-A Lee ,  Ho-Jin Cho ,  Young-Dae Kim ,  Jun-Soo Chang ,  Su-Jin Chae ,  Hai-Won Kim

    Inventor： Eun-A Lee ,  Ho-Jin Cho ,  Young-Dae Kim ,  Jun-Soo Chang ,  Su-Jin Chae ,  Hai-Won Kim

    IPC: H01G4/06

    CPC classification number: B82Y10/00 ,  H01G4/005 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer. The method includes the steps of: forming a conductive layer for forming a lower electrode; forming a nanotube array including a plurality of nanotubes formed on the conductive layer without using a catalytic layer; forming a dielectric layer on the nanotube array; and forming an upper electrode on the dielectric layer.

    Abstract translation: 提供了一种具有纳米管的电容器及其制造方法。 所述电容器包括：下电极，其包括图案化导电层和形成在所述图案化导电层上的多个纳米管，所述多个纳米管不需要使用催化剂层; 形成在下电极上的电介质层; 以及形成在电介质层上的上电极。 该方法包括以下步骤：形成用于形成下电极的导电层; 在不使用催化剂层的情况下形成包括形成在所述导电层上的多个纳米管的纳米管阵列; 在纳米管阵列上形成介电层; 以及在所述电介质层上形成上电极。

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