公开(公告)号：US06319765B1

公开(公告)日：2001-11-20

申请号：US09473107

申请日：1999-12-28

Applicant: Ho Jin Cho ,  Kwon Hong

Inventor： Ho Jin Cho ,  Kwon Hong

IPC: H01L218242

CPC classification number: H01L28/55 ,  C23C16/18 ,  H01L28/60

Abstract: The present invention provides a method for fabricating a ferroelectric memory device to reduce manufacturing cost and to obtain the electric characteristic of capacitor. The method comprises the steps of: forming an intermetal insulating layer provided with a contact hole exposing a junction region formed on a semiconductor layer having the junction region; forming a contact plug within the contact hole; forming a barrier layer and a metal layer for lower electrode on the intermetal insulating layer successively; forming a lower electrode by patterning selected portions of the metal layer for lower electrode and the barrier layer; forming a high dielectric layer on the substrate on which the lower electrode is formed; and forming an upper electrode on the high dielectric layer, wherein during forming the upper electrode, an F ion layer to be trapped by dangling bonds formed at an interface between the upper electrode and the high dielectric layer, is formed at the interface.

Abstract translation: 本发明提供一种制造铁电存储器件的方法，以降低制造成本并获得电容器的电特性。该方法包括以下步骤：形成金属间绝缘层，该金属间绝缘层设有暴露半导体上形成的结区的接触孔 层具有接合区域; 在所述接触孔内形成接触塞; 在金属间绝缘层上形成用于下电极的阻挡层和金属层; 通过图案化用于下电极和阻挡层的金属层的选定部分来形成下电极; 在其上形成下电极的基板上形成高介电层; 以及在所述高电介质层上形成上电极，其中在形成所述上电极期间，在所述界面处形成要被形成在所述上电极和所述高电介质层之间的界面处的悬挂键捕获的F离子层。

公开(公告)号：US08470668B2

公开(公告)日：2013-06-25

申请号：US12979926

申请日：2010-12-28

Applicant: Ho Jin Cho ,  Cheol Hwan Park ,  Dong Kyun Lee

Inventor： Ho Jin Cho ,  Cheol Hwan Park ,  Dong Kyun Lee

IPC: H01L21/8242

CPC classification number: H01L27/10894 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/90

Abstract: An embodiment of the invention includes a pillar type capacitor where a pillar is formed over an upper portion of a storage node contact. A bottom electrode is formed over sidewalls of the pillar, and a dielectric film is formed over pillar and the bottom electrode. A top electrode is then formed over the upper portion of the dielectric film.

Abstract translation: 本发明的实施例包括柱形电容器，其中柱形成在存储节点接触件的上部上。 底部电极形成在支柱的侧壁上，电介质膜形成在支柱和底部电极之上。 然后在电介质膜的上部上形成顶部电极。

公开(公告)号：US07985645B2

公开(公告)日：2011-07-26

申请号：US12649610

申请日：2009-12-30

Applicant: Cheol Hwan Park ,  Ho Jin Cho ,  Dong Kyun Lee

Inventor： Cheol Hwan Park ,  Ho Jin Cho ,  Dong Kyun Lee

IPC: H01L21/8242

CPC classification number: H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10894

Abstract: A semiconductor device having a high aspect cylindrical capacitor and a method for fabricating the same is presented. The high aspect cylindrical type capacitor is a stable structure which is not prone to causing bunker defects and losses in a guard ring. The semiconductor device includes the cylindrical type capacitor structure, a storage node oxide, a guard ring hole, a conductive layer, and a capping oxide. The cylindrical type capacitor structure in a cell region includes a cylindrical type lower electrode, a dielectric and an upper electrode. The storage node oxide is in a peripheral region over the semiconductor substrate. The conductive layer coating the guard ring hole. The guard ring hole at a boundary of the peripheral region that adjoins the cell region over the semiconductor substrate. The capping oxide partially fills in a part of the conductive layer. The gapfill film filling in the rest of the conductive layer.

Abstract translation: 提出了具有高方位圆柱形电容器的半导体器件及其制造方法。 高档圆柱型电容器是一种稳定的结构，不容易造成保护环中的掩体缺陷和损失。 半导体器件包括圆柱形电容器结构，存储节点氧化物，保护环孔，导电层和封盖氧化物。 单元区域中的圆柱型电容器结构包括圆筒形下电极，电介质和上电极。 存储节点氧化物位于半导体衬底上的周边区域中。 导电层涂覆保护环孔。 在与半导体基板上的单元区域相邻的周边区域的边界处的保护环孔。 覆盖氧化物部分地填充导电层的一部分。 间隙填充膜填充在导电层的其余部分。

公开(公告)号：US06355521B1

公开(公告)日：2002-03-12

申请号：US09659509

申请日：2000-09-11

Applicant: Ho Jin Cho

Inventor： Ho Jin Cho

IPC: H01L21336

CPC classification number: H01L28/60 ,  H01L21/31604 ,  H01L28/91

Abstract: The present invention discloses a method of manufacturing a capacitor in a semiconductor device which is directed to solve the problem of reduction of capacitance occurring when manufacturing a capacitor of a MIS structure using poly-silicon as an underlying electrode and metal as an upper electrode in a capacitor using Ta2O5 as a dielectric film. In order to solve the problem, the present invention forms an underlying electrode using metal having a good oxide-resistant such as TiSiN. Thus, the present invention could not only lower the thickness of the effective oxide film of Ta2O5 when depositing Ta2O5 or performing a thermal process for crystallization but also prevent increase of a leak current due to oxidization of the underlying electrode and the diffusion prevention film, thus securing the capacitance of the capacitor and improving the electric characteristic of the capacitor.

Abstract translation: 本发明公开了一种在半导体器件中制造电容器的方法，该方法旨在解决当制造使用多晶硅作为底层电极的MIS结构的电容器和在金属作为上部电极的金属制造时发生的电容减小的问题 电容器采用Ta2O5作为电介质膜。 为了解决这个问题，本发明利用TiSiN等具有良好的耐氧化性的金属形成下层电极。 因此，本发明不仅可以降低Ta2O5的有效氧化膜的厚度，还可以防止由于底层电极和扩散防止膜的氧化引起的漏电流的增加， 确保电容器的电容并改善电容器的电气特性。

公开(公告)号：US06306666B1

公开(公告)日：2001-10-23

申请号：US09461844

申请日：1999-12-15

Applicant: Ho Jin Cho

Inventor： Ho Jin Cho

IPC: H01G706

CPC classification number: H01L28/55 ,  H01L21/28568 ,  H01L21/31691 ,  H01L28/75

Abstract: The present invention provides a method for fabricating a ferroelectric memory device capable of preventing formation of an oxide layer between a BST layer and a storage node electrode with using a general electrode that is easy to etch, as a storage node electrode. The method comprises the steps of: forming successively a barrier layer and a metal layer for storage node electrode on the intermetal insulating layer; forming a storage node electrode by patterning the metal layer for storage node electrode and the barrier layer to be contact with the contact plug; depositing a ferroelectric layer on the storage node electrode and the intermetal insulating layer at a temperature that the storage node electrode is not oxidized; crystallizing the ferroelectric layer; and forming a plate electrode on the ferroelectric layer, wherein the ferroelectric layer is deposited at temperature of 100˜400° C. according to the MOCVD method.

Abstract translation: 本发明提供了一种制造铁电存储器件的方法，所述铁电存储器件能够防止在使用容易蚀刻的一般电极之间形成BST层和存储节点电极之间的氧化物层作为存储节点电极。该方法包括： 步骤：在金属间绝缘层上连续形成用于存储节点电极的阻挡层和金属层; 通过图案化用于存储节点电极的金属层和阻挡层与接触插塞接触来形成存储节点电极; 在存储节点电极未被氧化的温度下，在存储节点电极和金属间绝缘层上沉积铁电层; 结晶铁电层; 并在铁电层上形成平板电极，其中根据MOCVD方法在100〜400℃的温度下沉积铁电体层。

公开(公告)号：US08476688B2

公开(公告)日：2013-07-02

申请号：US12244115

申请日：2008-10-02

Applicant: Ho Jin Cho ,  Cheol Hwan Park ,  Jae Wook Seo ,  Jong Kuk Kim

Inventor： Ho Jin Cho ,  Cheol Hwan Park ,  Jae Wook Seo ,  Jong Kuk Kim

IPC: H01L31/113

CPC classification number: H01L28/91 ,  H01L27/10852

Abstract: A semiconductor device that prevents the leaning of storage node when forming a capacitor having high capacitance includes a plurality of cylinder-shaped storage nodes formed over a semiconductor substrate; and support patterns formed to fix the storage nodes in the form of an ‘L’ or a ‘+’ when viewed from the top. This semiconductor device having support patterns in the form of an ‘L’ or a ‘+’ reduces stress on the storage nodes when subsequently forming a dielectric layer and plate nodes that prevents the capacitors from leaking.

Abstract translation: 当形成具有高电容的电容器时，防止存储节点倾斜的半导体器件包括形成在半导体衬底上的多个圆柱形存储节点; 以及当从顶部观察时，形成为以“L”或“+”的形式固定存储节点的支撑图案。 具有“L”或“+”形式的支撑图案的这种半导体器件随后形成介电层并且防止电容器泄漏的板节点减小了存储节点上的应力。

公开(公告)号：US07871939B2

公开(公告)日：2011-01-18

申请号：US11966185

申请日：2007-12-28

Applicant: Gyu Dong Cho ,  Ho Jin Cho ,  Hyun Jung Kim

Inventor： Gyu Dong Cho ,  Ho Jin Cho ,  Hyun Jung Kim

IPC: H01L21/31

CPC classification number: H01L29/66621 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/3143

Abstract: A method for manufacturing a semiconductor device for use in avoiding unwanted oxidation along exposed surfaces and for use in relieving etching damage is presented. The method includes step of forming sequentially a gate insulation layer, a polysilicon layer, a barrier layer, a metallic layer and a hard mask layer over a semiconductor substrate. The method also includes a step of etching the hard mask layer, the metallic layer, the barrier layer, the polysilicon layer and the gate insulation layer to form a gate. The method also includes a nitrifying step which uses a free radical is assisted chemical vapor deposition (RACVD) nitrifying process on surfaces of the layers forming the gate and a surface of the semiconductor substrate. The method also includes a step of subsequently performing a reoxidation process to the semiconductor substrate resultant that the RACVD nitrifying process is performed.

Abstract translation: 本发明提供一种制造半导体器件的方法，该半导体器件用于避免暴露表面的不必要的氧化并用于缓解蚀刻损伤。 该方法包括在半导体衬底上依次形成栅极绝缘层，多晶硅层，势垒层，金属层和硬掩模层的步骤。 该方法还包括蚀刻硬掩模层，金属层，势垒层，多晶硅层和栅极绝缘层以形成栅极的步骤。 该方法还包括在形成栅极和半导体衬底的表面的表面上使用自由基辅助化学气相沉积（RACVD）硝化过程的硝化步骤。 该方法还包括随后对半导体衬底的再氧化过程产生RACVD硝化过程的步骤。

公开(公告)号：US07638407B2

公开(公告)日：2009-12-29

申请号：US12265759

申请日：2008-11-06

Applicant: Cheol Hwan Park ,  Ho Jin Cho ,  Jae Soo Kim ,  Dong Kyun Lee

Inventor： Cheol Hwan Park ,  Ho Jin Cho ,  Jae Soo Kim ,  Dong Kyun Lee

IPC: H01L21/20

CPC classification number: H01L28/91

Abstract: Forming a capacitor of a semiconductor device includes forming an interlayer dielectric having holes over a semiconductor substrate. A conductive layer is then formed on surfaces of the holes and on the upper surface of the interlayer dielectric. A silicon-containing conductive layer is formed by flowing a silicon source gas for the semiconductor substrate formed with the conductive layer, so that silicon atoms can penetrate into the conductive layer. The silicon-containing conductive layer prevents etchant from infiltrating the interlayer dielectric below the silicon-containing conductive layer.

Abstract translation: 形成半导体器件的电容器包括在半导体衬底上形成具有孔的层间电介质。 然后在孔的表面和层间电介质的上表面上形成导电层。 通过使形成有导电层的半导体衬底的硅源气体流动而形成含硅导电层，使得硅原子能够渗透到导电层中。 含硅导电层防止蚀刻剂渗透到含硅导电层之下的层间电介质。

公开(公告)号：US07576383B2

公开(公告)日：2009-08-18

申请号：US11779093

申请日：2007-07-17

Applicant: Ho Jin Cho ,  Cheol Hwan Park ,  Jae Soo Kim ,  Dong Kyun Lee

Inventor： Ho Jin Cho ,  Cheol Hwan Park ,  Jae Soo Kim ,  Dong Kyun Lee

IPC: H01L27/108

CPC classification number: H01L28/65 ,  H01L27/10852 ,  H01L28/91

Abstract: A capacitor is made by forming a buffer oxide layer, an etching stop layer, and a mold insulation layer over a semiconductor substrate having a storage node contact plug. The mold insulation layer and the etching stop layer are etched to form a hole in an upper portion of the storage node contact plug. A tapering layer is deposited over the mold insulation layer including the hole. The tapering layer and the buffer oxide layer are etched back so that the tapering layer is remained only at the upper end portion of the etched hole. A metal storage node layer formed on the etched hole over the remaining tapering layer. The mold insulation layer and the remaining tapering layer are removed to form a cylindrical storage node having a tapered upper end. A dielectric layer and a plate node are formed over the storage node.

Abstract translation: 通过在具有存储节点接触插塞的半导体衬底上形成缓冲氧化物层，蚀刻停止层和模具绝缘层来制造电容器。 蚀刻模具绝缘层和蚀刻停止层，以在存储节点接触插塞的上部形成孔。 在包括孔的模具绝缘层上沉积渐缩层。 锥形层和缓冲氧化物层被回蚀刻，使得锥形层仅保留在蚀刻孔的上端部。 在剩余的锥形层上形成在蚀刻孔上的金属储存节点层。 去除模具绝缘层和剩余的锥形层以形成具有锥形上端的圆柱形存储节点。 在存储节点上形成介电层和板状节点。

公开(公告)号：US20070264770A1

公开(公告)日：2007-11-15

申请号：US11618796

申请日：2006-12-30

Applicant: Keum Bum Lee ,  Hai Won Kim ,  Ho Jin Cho ,  Jun Soo Chang ,  Eun A. Lee ,  Dong Su Park

Inventor： Keum Bum Lee ,  Hai Won Kim ,  Ho Jin Cho ,  Jun Soo Chang ,  Eun A. Lee ,  Dong Su Park

IPC: H01L21/8242 ,  H01L29/92

CPC classification number: H01L21/3141 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/0234 ,  H01L27/10852 ,  H01L28/91

Abstract: A method for forming a capacitor includes forming a concave mold over a semiconductor substrate. A storage node is formed on the concave mold. A dielectric layer including a zirconium oxide (ZrO2) layer is deposited over the storage node at a first temperature. A radical pile-up treatment on the dielectric layer is performed in an atmosphere including radicals at a second temperature higher than the first temperature to induce crystallization of the dielectric layer. A plate node is formed over the dielectric layer.

Abstract translation: 形成电容器的方法包括在半导体衬底上形成凹模。 存储节点形成在凹模上。 包含氧化锆（ZrO 2）层的电介质层在第一温度下沉积在存储节点上。 在包括自由基的气氛中，在高于第一温度的第二温度下进行介电层上的自由基堆积处理，以诱导电介质层的结晶。 在该电介质层上形成一个平板节点。