公开(公告)号：US06319765B1

公开(公告)日：2001-11-20

申请号：US09473107

申请日：1999-12-28

Applicant: Ho Jin Cho ,  Kwon Hong

Inventor： Ho Jin Cho ,  Kwon Hong

IPC: H01L218242

CPC classification number: H01L28/55 ,  C23C16/18 ,  H01L28/60

Abstract: The present invention provides a method for fabricating a ferroelectric memory device to reduce manufacturing cost and to obtain the electric characteristic of capacitor. The method comprises the steps of: forming an intermetal insulating layer provided with a contact hole exposing a junction region formed on a semiconductor layer having the junction region; forming a contact plug within the contact hole; forming a barrier layer and a metal layer for lower electrode on the intermetal insulating layer successively; forming a lower electrode by patterning selected portions of the metal layer for lower electrode and the barrier layer; forming a high dielectric layer on the substrate on which the lower electrode is formed; and forming an upper electrode on the high dielectric layer, wherein during forming the upper electrode, an F ion layer to be trapped by dangling bonds formed at an interface between the upper electrode and the high dielectric layer, is formed at the interface.

Abstract translation: 本发明提供一种制造铁电存储器件的方法，以降低制造成本并获得电容器的电特性。该方法包括以下步骤：形成金属间绝缘层，该金属间绝缘层设有暴露半导体上形成的结区的接触孔 层具有接合区域; 在所述接触孔内形成接触塞; 在金属间绝缘层上形成用于下电极的阻挡层和金属层; 通过图案化用于下电极和阻挡层的金属层的选定部分来形成下电极; 在其上形成下电极的基板上形成高介电层; 以及在所述高电介质层上形成上电极，其中在形成所述上电极期间，在所述界面处形成要被形成在所述上电极和所述高电介质层之间的界面处的悬挂键捕获的F离子层。

公开(公告)号：US08288819B2

公开(公告)日：2012-10-16

申请号：US12953255

申请日：2010-11-23

Applicant: Yong Soo Kim ,  Hong Seon Yang ,  Se Aug Jang ,  Seung Ho Pyi ,  Kwon Hong ,  Heung Jae Cho ,  Kwan Yong Lim ,  Min Gyu Sung ,  Seung Ryong Lee ,  Tae Yoon Kim

Inventor： Yong Soo Kim ,  Hong Seon Yang ,  Se Aug Jang ,  Seung Ho Pyi ,  Kwon Hong ,  Heung Jae Cho ,  Kwan Yong Lim ,  Min Gyu Sung ,  Seung Ryong Lee ,  Tae Yoon Kim

IPC: H01L21/336

CPC classification number: H01L29/66553 ,  H01L27/10876 ,  H01L29/518 ,  H01L29/66621

Abstract: A method for fabricating a semiconductor device includes providing a substrate having a bulb-type recessed region, forming a gate insulating layer over the bulb-type recessed region and the substrate, and forming a gate conductive layer over the gate insulating layer. The gate conductive layer fills the bulb-type recessed region. The gate conductive layer includes two or more conductive layers and a discontinuous interface between the conductive layers.

Abstract translation: 一种制造半导体器件的方法，包括提供具有灯泡型凹陷区域的衬底，在灯泡型凹陷区域上形成栅极绝缘层和衬底，并在栅极绝缘层上形成栅极导电层。 栅极导电层填充灯泡型凹陷区域。 栅极导电层包括两个或多个导电层和导电层之间的不连续界面。

公开(公告)号：US20120168850A1

公开(公告)日：2012-07-05

申请号：US13310329

申请日：2011-12-02

Applicant: Ki-Hong LEE ,  Kwon Hong ,  Beom-yong Kim

Inventor： Ki-Hong LEE ,  Kwon Hong ,  Beom-yong Kim

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L27/11578 ,  H01L27/11575 ,  H01L27/11582

Abstract: A nonvolatile memory device includes a channel protruding in a vertical direction from a substrate, a plurality of interlayer dielectric layers and gate electrode layers which are alternately stacked over the substrate along the channel, and a memory layer formed between the channel and a stacked structure of the interlayer dielectric layers and gate electrode layers. Two or more gate electrode layers of the plurality of gate electrode layers are coupled to an interconnection line to form a selection transistor.

Abstract translation: 非易失性存储器件包括沿着垂直方向从衬底突出的沟道，多个层间电介质层和栅极电极层，沿着沟道交替堆叠在衬底上;以及存储层，形成在沟道和层叠结构之间 层间电介质层和栅电极层。 多个栅电极层中的两个或多个栅电极层耦合到互连线以形成选择晶体管。

公开(公告)号：US20110291176A1

公开(公告)日：2011-12-01

申请号：US12850765

申请日：2010-08-05

Applicant: Ki-Hong Lee ,  Moon-Sig Joo ,  Kwon Hong

Inventor： Ki-Hong Lee ,  Moon-Sig Joo ,  Kwon Hong

IPC: H01L29/792 ,  H01L21/28

CPC classification number: H01L29/792 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

Abstract: A non-volatile memory device includes a pair of columnar cell channels vertically extending from a substrate, a doped pipe channel arranged to couple lower ends of the pair of columnar cell channels, insulation layers over the substrate in which the doped pipe channel is buried, memory layers arranged to surround side surfaces of the columnar cell channels, and control gate electrodes arranged to surround the memory layers.

Abstract translation: 非易失性存储器件包括从衬底垂直延伸的一对柱状单元通道，布置成耦合该对柱状单元通道的下端的掺杂管道，在其上埋入掺杂管道的衬底上的绝缘层， 布置成围绕柱状单元通道的侧表面的存储层以及布置成围绕存储层的控制栅电极。

公开(公告)号：US20090163015A1

公开(公告)日：2009-06-25

申请号：US12147178

申请日：2008-06-26

Applicant: Eun Shil Park ,  Kwon Hong ,  Jae Hong Kim ,  Jae Hyoung Koo

Inventor： Eun Shil Park ,  Kwon Hong ,  Jae Hong Kim ,  Jae Hyoung Koo

IPC: H01L21/28

CPC classification number: H01L21/28273 ,  H01L27/11521

Abstract: The present invention relates to a method of fabricating a flash memory device. According to a method of fabricating a flash memory device in accordance with an aspect of the present invention, a semiconductor substrate over which a tunnel insulating layer and a first conductive layer are formed is provided. A first oxide layer is formed on the first conductive layer using a plasma oxidization process in a state where a back bias voltage is applied. A nitride layer is formed on the first oxide layer. A second oxide layer is formed on the nitride layer. A second conductive layer is formed on the second oxide layer.

Abstract translation: 本发明涉及一种制造闪速存储器件的方法。 根据本发明的一个方面的制造闪速存储器件的方法，提供了形成隧道绝缘层和第一导电层的半导体衬底。 在施加反向偏置电压的状态下，使用等离子体氧化工艺在第一导电层上形成第一氧化物层。 在第一氧化物层上形成氮化物层。 在氮化物层上形成第二氧化物层。 在第二氧化物层上形成第二导电层。

公开(公告)号：US20090068850A1

公开(公告)日：2009-03-12

申请号：US12147802

申请日：2008-06-27

Applicant: Jae Hyoung Koo ,  Kwon Hong ,  Jae Hong Kim ,  Eun Shil Park

Inventor： Jae Hyoung Koo ,  Kwon Hong ,  Jae Hong Kim ,  Eun Shil Park

IPC: H01L21/283

CPC classification number: H01L21/0214 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/31662 ,  H01L29/66833

Abstract: The present invention relates generally to a method of fabricating a flash memory device. The method includes forming a tunnel dielectric layer on a semiconductor substrate using a plasma oxidization process. The tunnel dielectric layer is formed using the plasma oxidation process employing Ar and O2 gases, therefore, defect charges can be prevented from being created due to dangling bonds such as Si—H. Accordingly, the shift of the threshold voltage (Vth) of a device can be reduced and cycling and charge retention characteristics can be improved.

Abstract translation: 本发明一般涉及制造闪速存储器件的方法。 该方法包括使用等离子体氧化工艺在半导体衬底上形成隧道介电层。 使用Ar和O 2气体的等离子体氧化工艺形成隧道介电层，因此可以防止由于诸如Si-H的悬挂键而产生缺陷电荷。 因此，可以降低器件的阈值电压（Vth）的偏移，并且可以提高循环和电荷保持特性。

公开(公告)号：US07446053B2

公开(公告)日：2008-11-04

申请号：US11326064

申请日：2005-12-30

Applicant: Deok-Sin Kil ,  Kwon Hong ,  Seung-Jin Yeom

Inventor： Deok-Sin Kil ,  Kwon Hong ,  Seung-Jin Yeom

IPC: H01L21/28 ,  H01L21/44

CPC classification number: H01G4/1218 ,  H01G4/12 ,  H01G4/1236 ,  H01G4/206 ,  H01L28/40 ,  Y10S977/70 ,  Y10S977/902

Abstract: A capacitor with a nano-composite dielectric layer and a method for fabricating the same are provided. A dielectric layer of a capacitor includes a nano-composite layer formed by mixing X number of different sub-layers, X being a positive integer greater than approximately 1. A method for forming a dielectric layer of a capacitor includes: forming a nano-composite layer by mixing X number of different sub-layers in the form of a nano-composition, X being a positive integer greater than approximately 1; and densifying the nano-composite layer.

Abstract translation: 提供具有纳米复合介电层的电容器及其制造方法。 电容器的电介质层包括通过混合X个不同子层形成的纳米复合层，X是大于约1的正整数。形成电容器的电介质层的方法包括：形成纳米复合材料 通过以纳米组合物的形式混合X个不同子层的X层，X为大于约1的正整数; 并使纳米复合层致密化。

公开(公告)号：US20080160748A1

公开(公告)日：2008-07-03

申请号：US11954673

申请日：2007-12-12

Applicant: Kwon Hong ,  Dong Ho Lee ,  Jae Mun Kim ,  Hee Soo Kim ,  Jae Hyoung Koo

Inventor： Kwon Hong ,  Dong Ho Lee ,  Jae Mun Kim ,  Hee Soo Kim ,  Jae Hyoung Koo

IPC: H01L21/283

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L29/513 ,  H01L29/7881

Abstract: The present invention relates to a method of forming a dielectric layer of a flash memory device. In a process of forming a dielectric layer of a flash memory device, the dielectric layer may include a first oxide layer, a high dielectric layer, and a second oxide layer is formed. Accordingly, a leakage current characteristic and reliability of the flash memory device can be improved.

Abstract translation: 本发明涉及一种形成闪存器件的电介质层的方法。 在形成闪速存储器件的电介质层的过程中，介电层可以包括第一氧化物层，高电介质层和形成第二氧化物层。 因此，可以提高闪存器件的漏电流特性和可靠性。

公开(公告)号：US20070001201A1

公开(公告)日：2007-01-04

申请号：US11326064

申请日：2005-12-30

Applicant: Deok-Sin Kil ,  Kwon Hong ,  Seung-Jin Yeom

Inventor： Deok-Sin Kil ,  Kwon Hong ,  Seung-Jin Yeom

IPC: H01L29/94 ,  H01L29/00

CPC classification number: H01G4/1218 ,  H01G4/12 ,  H01G4/1236 ,  H01G4/206 ,  H01L28/40 ,  Y10S977/70 ,  Y10S977/902

Abstract: A capacitor with a nano-composite dielectric layer and a method for fabricating the same are provided. A dielectric layer of a capacitor includes a nano-composite layer formed by mixing X number of different sub-layers, X being a positive integer greater than approximately 1. A method for forming a dielectric layer of a capacitor includes: forming a nano-composite layer by mixing X number of different sub-layers in the form of a nano-composition, X being a positive integer greater than approximately 1; and densifying the nano-composite layer.

Abstract translation: 提供具有纳米复合介电层的电容器及其制造方法。 电容器的电介质层包括通过混合X个不同子层形成的纳米复合层，X是大于约1的正整数。形成电容器的电介质层的方法包括：形成纳米复合材料 通过以纳米组合物的形式混合X个不同子层的X层，X为大于约1的正整数; 并使纳米复合层致密化。

公开(公告)号：US20060183301A1

公开(公告)日：2006-08-17

申请号：US11321538

申请日：2005-12-30

Applicant: Seung-Jin Yeom ,  Deok-Sin Kil ,  Kwon Hong ,  Jae-Sung Roh

Inventor： Seung-Jin Yeom ,  Deok-Sin Kil ,  Kwon Hong ,  Jae-Sung Roh

IPC: H01L21/20

CPC classification number: C23C16/45525 ,  C23C16/45527 ,  C23C16/45542 ,  H01L21/28562 ,  H01L21/3141 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/65 ,  H01L28/91

Abstract: A method for forming a thin film by using an atomic layer deposition (ALD) method and a method for fabricating a capacitor using the same includes: supplying a source gas, a reaction gas, and a purge gas, then discontinuing the supply of the reaction gas and the source gas, followed by supplying and then discontinuing the supply of the reaction gas, wherein supplying the source gas, the reaction gas, and the purge gas, then discontinuing the supply of the reaction gas and the source gas, followed by supplying and then discontinuing the supply of the reaction gas constitutes a unit cycle, and repeating the unit cycle until a thin film having a desired thickness is deposited.

Abstract translation: 通过使用原子层沉积（ALD）法和使用其制造电容器的方法形成薄膜的方法包括：供应源气体，反应气体和吹扫气体，然后停止反应的供应 气体和源气体，然后供应然后停止反应气体的供应，其中供应源气体，反应气体和吹扫气体，然后停止反应气体和源气体的供应，然后供应 然后停止反应气体的供给构成单位循环，并重复单位循环，直到沉积具有期望厚度的薄膜。