公开(公告)号：US07030635B2

公开(公告)日：2006-04-18

申请号：US10893341

申请日：2004-07-19

Applicant: Gwan-pyo Hong ,  Hyong-yong Lee

Inventor： Gwan-pyo Hong ,  Hyong-yong Lee

IPC: G01R31/02

CPC classification number: G01R25/00

Abstract: A device for measuring voltage, including a voltage detecting portion for detecting a plurality of voltages and outputting a maximum voltage of the plurality of voltages, a voltage latching portion that receives a first output from the voltage detecting portion, and a voltage reading portion that receives a second output from the voltage latching portion. Another device for measuring voltage, including a supply voltage, a ground voltage, and first and second supply voltage measuring units connected in parallel to each other between the supply voltage and the ground voltage. A method for measuring voltage, including receiving a plurality of voltages, detecting a maximum voltage from the plurality of voltages, maintaining the detected maximum voltage, and outputting the maintained detected maximum voltage.

Abstract translation: 一种用于测量电压的装置，包括用于检测多个电压并输出多个电压的最大电压的电压检测部分，接收来自电压检测部分的第一输出的电压锁存部分和接收电压检测部分的电压读取部分 来自电压锁存部分的第二输出。 用于测量电压的另一个装置，包括电源电压，接地电压以及在电源电压和接地电压之间并联连接的第一和第二电源电压测量单元。 一种用于测量电压的方法，包括接收多个电压，从多个电压检测最大电压，维持检测到的最大电压，并输出维持的检测到的最大电压。

公开(公告)号：US20050104611A1

公开(公告)日：2005-05-19

申请号：US10893341

申请日：2004-07-19

Applicant: Gwan-pyo Hong ,  Hyong-yong Lee

Inventor： Gwan-pyo Hong ,  Hyong-yong Lee

IPC: G01R31/26 ,  G01R19/165 ,  G01R25/00 ,  G01R31/30 ,  G11C5/14 ,  G01R31/02

CPC classification number: G01R25/00

Abstract: A device for measuring voltage, including a voltage detecting portion for detecting a plurality of voltages and outputting a maximum voltage of the plurality of voltages, a voltage latching portion that receives a first output from the voltage detecting portion, and a voltage reading portion that receives a second output from the voltage latching portion. Another device for measuring voltage, including a supply voltage, a ground voltage, and first and second supply voltage measuring units connected in parallel to each other between the supply voltage and the ground voltage. A method for measuring voltage, including receiving a plurality of voltages, detecting a maximum voltage from the plurality of voltages, maintaining the detected maximum voltage, and outputting the maintained detected maximum voltage.

Abstract translation: 一种用于测量电压的装置，包括用于检测多个电压并输出多个电压的最大电压的电压检测部分，接收来自电压检测部分的第一输出的电压锁存部分和接收电压检测部分的电压读取部分 来自电压锁存部分的第二输出。 用于测量电压的另一个装置，包括电源电压，接地电压以及在电源电压和接地电压之间并联连接的第一和第二电源电压测量单元。 一种用于测量电压的方法，包括接收多个电压，从多个电压检测最大电压，维持检测到的最大电压，并输出维持的检测到的最大电压。

公开(公告)号：US06252441B1

公开(公告)日：2001-06-26

申请号：US09585443

申请日：2000-06-02

Applicant: Hyong-yong Lee ,  Sang-chul Kim

Inventor： Hyong-yong Lee ,  Sang-chul Kim

IPC: H03L700

CPC classification number: G11C7/1093 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22

Abstract: A synchronous data sampling circuit and method are provided by which it is possible to sample four data items during one cycle of a clock signal. In the synchronous data sampling circuit a first pulse signal generator receives the clock signal and generates a first pulse signal during a logic “low” interval of the clock signal. A second pulse signal generator receives the clock signal and generates a second pulse signal during a logic “high” interval of the clock signal. A first sampling unit samples first data input through the input port and outputs the sampled first data to the output port in response to the falling edge of the clock signal. A second sampling unit samples second data input through the input port and outputs the sampled second data to the output port in response to a rising or falling edge of the first pulse signal. A third sampling unit samples third data input through the input port and outputs the sampled third data to the output port in response to the rising edge of the clock signal. A fourth sampling unit samples fourth data input through the input port and outputs the sampled fourth data to the output port in response to the rising or falling edge of the second pulse signal. As a result, four data items are sampled during one cycle of the clock signal, doubling the data sampling efficiency, as compared to the data sampling efficiency of a conventional dual data rate (DDR) method.

Abstract translation: 提供了一种同步数据采样电路和方法，通过该方法可以在时钟信号的一个周期期间对四个数据项进行采样。 在同步数据采样电路中，第一脉冲信号发生器在时钟信号的逻辑“低”间隔期间接收时钟信号并产生第一脉冲信号。 第二脉冲信号发生器在时钟信号的逻辑“高”间隔期间接收时钟信号并产生第二脉冲信号。 第一采样单元对通过输入端口输入的第一数据进行采样，并响应于时钟信号的下降沿将采样的第一数据输出到输出端口。 第二采样单元通过输入端口采样第二数据输入，并响应于第一脉冲信号的上升沿或下降沿将采样的第二数据输出到输出端口。 第三采样单元对通过输入端口输入的第三数据进行采样，并响应于时钟信号的上升沿将采样的第三数据输出到输出端口。 第四采样单元对通过输入端口输入的第四数据进行采样，并响应于第二脉冲信号的上升沿或下降沿将采样的第四数据输出到输出端口。 结果，与传统双数据速率（DDR）方法的数据采样效率相比，在时钟信号的一个周期期间对四个数据项进行采样，使数据采样效率翻倍。

公开(公告)号：US20070008810A1

公开(公告)日：2007-01-11

申请号：US11481187

申请日：2006-07-06

Applicant: Hyong-Yong Lee

Inventor： Hyong-Yong Lee

IPC: G11C8/18

CPC classification number: G11C7/1045 ,  G11C7/1066 ,  G11C29/46

Abstract: Mode register setting methods and apparatuses for semiconductor devices are provided in order to suppress a limit in the frequency at which a mode register of a semiconductor device operates from occurring before the semiconductor device carries out a typical write or read operation, as the frequency at which the semiconductor device operates increases. The mode register setting methods and apparatuses may be applied, for example, to DDR-type semiconductor devices. If a chip selection signal /CS maintains a logic low level for at least a first amount of time, a semiconductor device may initiate a clock-independent mode register setting operation. In the clock-independent mode register setting operation, a mode register set (MRS) command and an MRS code bit may be sampled when the logic level of a data strobe signal applied to the semiconductor device transitions from a logic low level to a logic high level. Therefore, it is possible to solve the problem of restrictions regarding the operating frequency of the mode register of the semiconductor device by performing a test mode register setting operation independent of a clock signal applied to the semiconductor device.

Abstract translation: 提供了用于半导体器件的模式寄存器设置方法和装置，以便抑制半导体器件的模式寄存器在半导体器件执行典型的写入或读取操作之前发生的模式寄存器的频率的限制，作为其中 半导体器件工作增加。 模式寄存器设置方法和装置可以应用于例如DDR型半导体器件。 如果芯片选择信号/ CS至少保持第一时间的逻辑低电平，则半导体器件可以启动与时钟无关的模式寄存器设置操作。 在时钟独立模式寄存器设置操作中，当施加到半导体器件的数据选通信号的逻辑电平从逻辑低电平转换到逻辑高电平时，可以采样模式寄存器组（MRS）命令和MRS码位 水平。 因此，可以通过执行独立于施加到半导体器件的时钟信号的测试模式寄存器设置操作来解决关于半导体器件的模式寄存器的工作频率的限制的问题。

公开(公告)号：US07791960B2

公开(公告)日：2010-09-07

申请号：US12049160

申请日：2008-03-14

Applicant: Chung-Ki Lee ,  Hyong-Yong Lee

Inventor： Chung-Ki Lee ,  Hyong-Yong Lee

IPC: G11C7/00

CPC classification number: G11C7/24 ,  G11C5/143 ,  G11C7/22 ,  G11C29/02 ,  G11C29/021 ,  G11C29/023 ,  G11C29/028

Abstract: A semiconductor memory device and a control signal generating method thereof. The semiconductor memory device may include a voltage range detector configured to generate a voltage detecting signal corresponding to a range of a level of an external power voltage. A control signal generating portion may be used to generate a control signal corresponding to the range of the level of the external power voltage responsive to the voltage detecting signal. As a result, the semiconductor memory device can perform an operation for satisfying an access time characteristic according to a specification responsive to the control signal.

Abstract translation: 半导体存储器件及其控制信号产生方法。 半导体存储器件可以包括电压范围检测器，其被配置为产生对应于外部电源电压的电平的范围的电压检测信号。 可以使用控制信号产生部分来响应于电压检测信号产生对应于外部电源电压的电平的范围的控制信号。 结果，半导体存储器件可以响应于控制信号执行满足访问时间特性的操作。

公开(公告)号：US07551499B2

公开(公告)日：2009-06-23

申请号：US11803454

申请日：2007-05-15

Applicant: Hyong-yong Lee

Inventor： Hyong-yong Lee

IPC: G11C29/04

CPC classification number: G11C29/14 ,  G11C7/22 ,  G11C7/222 ,  G11C29/12015

Abstract: A semiconductor memory device and a method for testing the same are capable of performing a low-frequency test operation even when a high-frequency external clock signal is input. The method for testing the semiconductor memory device comprises: interpreting a control command from a plurality of external control signals and generating a low-frequency operation control signal when an MRS command included in the control command designates a write and read test operation; when a write command is input as the control command, converting the write command into a low-frequency write command in response to the low-frequency operation control signal, generating an internal low-frequency clock signal in response to the low-frequency operation control signal, and performing a low-frequency write operation based on the internal low-frequency clock signal; and buffering an external clock signal to generate an internal normal-frequency clock signal and, when a read command is input as the control command, performing a read operation based on the internal normal-frequency clock signal in response to the read command.

Abstract translation: 半导体存储器件及其测试方法即使在输入高频外部时钟信号时也能执行低频测试操作。 用于测试半导体存储器件的方法包括：当包括在控制命令中的MRS命令指定写入和读取测试操作时，解释来自多个外部控制信号的控制命令并产生低频操作控制信号; 当写命令被输入作为控制命令时，响应于低频操作控制信号将写入命令转换成低频写入命令，响应于低频操作控制产生内部低频时钟信号 信号，并且基于内部低频时钟信号执行低频写入操作; 并且缓冲外部时钟信号以产生内部正常频率时钟信号，并且当输入读取命令作为控制命令时，响应于读取命令，基于内部正常频率时钟信号执行读取操作。

公开(公告)号：US06396754B1

公开(公告)日：2002-05-28

申请号：US09901050

申请日：2001-07-10

Applicant: Hyong-yong Lee ,  Suk-bae Jun ,  Choong-sun Park

Inventor： Hyong-yong Lee ,  Suk-bae Jun ,  Choong-sun Park

IPC: G11C2900

CPC classification number: G11C29/02

Abstract: In a sense amplifier control circuit and method for a semiconductor memory device, a row address strobe (RAS) signal delay unit delays a RAS signal for a predetermined period of time. A sense amplifier control signal generator generates first and second sense amplifier control signals, responsive to the delayed RAS signal and a test mode control signal, which are enabled at the same time or at different periods depending on operation modes of the memory device. First and second sense amplifiers respectively sense and amplify the potential of odd-numbered and even-numbered bit line pairs of the memory device, responsive to the first and second sense amplifier control signals. The probability and accuracy of detecting bit line bridge defects are increased, because the times for sensing two adjacent bit lines are different.