公开(公告)号：US07525339B2

公开(公告)日：2009-04-28

申请号：US11717959

申请日：2007-03-14

Applicant: Hyong-yong Lee

Inventor： Hyong-yong Lee

IPC: H03K17/16

CPC classification number: H03K19/0005 ,  H04L25/0278

Abstract: A semiconductor memory device for testing whether an ODT circuit is on or off during a data read mode includes an on-die termination (ODT) circuit and an ODT state information output unit. The ODT circuit includes at least one ODT resistor. The ODT state information output unit outputs an ODT state information signal indicating whether the ODT circuit is on or off, in response to an ODT control signal during a data read mode when data is output from memory cells. With a semiconductor memory device and method capable of testing whether an ODT resistor is on or off during a data read mode, it is possible to test whether an ODT circuit is on or off during reading of data.

Abstract translation: 用于在数据读取模式期间测试ODT电路是开启还是关闭的半导体存储器件包括管芯端接（ODT）电路和ODT状态信息输出单元。 ODT电路包括至少一个ODT电阻。 ODT状态信息输出单元响应于当从存储器单元输出数据时在数据读取模式期间的ODT控制信号，输出指示ODT电路是开或关的ODT状态信息信号。 利用在数据读取模式期间能够测试ODT电阻是开或关的半导体存储器件和方法，可以在数据读取期间测试ODT电路是开或关。

公开(公告)号：US20080205174A1

公开(公告)日：2008-08-28

申请号：US12071552

申请日：2008-02-22

Applicant: Hyong-yong Lee ,  Chan-sub Jun

Inventor： Hyong-yong Lee ,  Chan-sub Jun

IPC: G11C29/00

CPC classification number: G11C29/32 ,  G11C11/401 ,  G11C29/14

Abstract: Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data groups at a first data rate on an external terminal. In a test mode of operation, the output circuit outputs the first data group or the second data group at a second data rate on the external terminal in response to control signals, without switching the test mode. The second data rate may be lower than the first data rate.

Abstract translation: 实施例公开半导体存储器件及其测试方法。 半导体存储器件包括在正常工作模式下以第一数据速率提供第一和第二数据组的存储单元阵列和输出电路，在外部端子上以第一数据速率串行输出第一和第二数据组 。 在测试操作模式下，输出电路响应于控制信号以外部终端的第二数据速率输出第一数据组或第二数据组，而不切换测试模式。 第二数据速率可能低于第一数据速率。

公开(公告)号：US07551499B2

公开(公告)日：2009-06-23

申请号：US11803454

申请日：2007-05-15

Applicant: Hyong-yong Lee

Inventor： Hyong-yong Lee

IPC: G11C29/04

CPC classification number: G11C29/14 ,  G11C7/22 ,  G11C7/222 ,  G11C29/12015

Abstract: A semiconductor memory device and a method for testing the same are capable of performing a low-frequency test operation even when a high-frequency external clock signal is input. The method for testing the semiconductor memory device comprises: interpreting a control command from a plurality of external control signals and generating a low-frequency operation control signal when an MRS command included in the control command designates a write and read test operation; when a write command is input as the control command, converting the write command into a low-frequency write command in response to the low-frequency operation control signal, generating an internal low-frequency clock signal in response to the low-frequency operation control signal, and performing a low-frequency write operation based on the internal low-frequency clock signal; and buffering an external clock signal to generate an internal normal-frequency clock signal and, when a read command is input as the control command, performing a read operation based on the internal normal-frequency clock signal in response to the read command.

Abstract translation: 半导体存储器件及其测试方法即使在输入高频外部时钟信号时也能执行低频测试操作。 用于测试半导体存储器件的方法包括：当包括在控制命令中的MRS命令指定写入和读取测试操作时，解释来自多个外部控制信号的控制命令并产生低频操作控制信号; 当写命令被输入作为控制命令时，响应于低频操作控制信号将写入命令转换成低频写入命令，响应于低频操作控制产生内部低频时钟信号 信号，并且基于内部低频时钟信号执行低频写入操作; 并且缓冲外部时钟信号以产生内部正常频率时钟信号，并且当输入读取命令作为控制命令时，响应于读取命令，基于内部正常频率时钟信号执行读取操作。

公开(公告)号：US06396754B1

公开(公告)日：2002-05-28

申请号：US09901050

申请日：2001-07-10

Applicant: Hyong-yong Lee ,  Suk-bae Jun ,  Choong-sun Park

Inventor： Hyong-yong Lee ,  Suk-bae Jun ,  Choong-sun Park

IPC: G11C2900

CPC classification number: G11C29/02

Abstract: In a sense amplifier control circuit and method for a semiconductor memory device, a row address strobe (RAS) signal delay unit delays a RAS signal for a predetermined period of time. A sense amplifier control signal generator generates first and second sense amplifier control signals, responsive to the delayed RAS signal and a test mode control signal, which are enabled at the same time or at different periods depending on operation modes of the memory device. First and second sense amplifiers respectively sense and amplify the potential of odd-numbered and even-numbered bit line pairs of the memory device, responsive to the first and second sense amplifier control signals. The probability and accuracy of detecting bit line bridge defects are increased, because the times for sensing two adjacent bit lines are different.

公开(公告)号：US08243540B2

公开(公告)日：2012-08-14

申请号：US13137768

申请日：2011-09-12

Applicant: Hyong-yong Lee ,  Chan-sub Jun

Inventor： Hyong-yong Lee ,  Chan-sub Jun

IPC: G11C7/00

CPC classification number: G11C29/32 ,  G11C11/401 ,  G11C29/14

Abstract: Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data groups at a first data rate on an external terminal. In a test mode of operation, the output circuit outputs the first data group or the second data group at a second data rate on the external terminal in response to control signals, without switching the test mode. The second data rate may be lower than the first data rate.

公开(公告)号：US20120014189A1

公开(公告)日：2012-01-19

申请号：US13137768

申请日：2011-09-12

Applicant: Hyong-yong Lee ,  Chan-sub Jun

Inventor： Hyong-yong Lee ,  Chan-sub Jun

IPC: G11C29/00

CPC classification number: G11C29/32 ,  G11C11/401 ,  G11C29/14

Abstract: Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data groups at a first data rate on an external terminal. In a test mode of operation, the output circuit outputs the first data group or the second data group at a second data rate on the external terminal in response to control signals, without switching the test mode. The second data rate may be lower than the first data rate.

Abstract translation: 实施例公开半导体存储器件及其测试方法。 半导体存储器件包括在正常工作模式下以第一数据速率提供第一和第二数据组的存储单元阵列和输出电路，在外部端子上以第一数据速率串行输出第一和第二数据组 。 在测试操作模式下，输出电路响应于控制信号以外部终端的第二数据速率输出第一数据组或第二数据组，而不切换测试模式。 第二数据速率可能低于第一数据速率。

公开(公告)号：US08036052B2

公开(公告)日：2011-10-11

申请号：US12071552

申请日：2008-02-22

Applicant: Hyong-yong Lee ,  Chan-sub Jun

Inventor： Hyong-yong Lee ,  Chan-sub Jun

IPC: G11C7/00

CPC classification number: G11C29/32 ,  G11C11/401 ,  G11C29/14

Abstract: Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data groups at a first data rate on an external terminal. In a test mode of operation, the output circuit outputs the first data group or the second data group at a second data rate on the external terminal in response to control signals, without switching the test mode. The second data rate may be lower than the first data rate.

Abstract translation: 实施例公开半导体存储器件及其测试方法。 半导体存储器件包括在正常工作模式下以第一数据速率提供第一和第二数据组的存储单元阵列和输出电路，在外部端子上以第一数据速率串行输出第一和第二数据组 。 在测试操作模式下，输出电路响应于控制信号以外部终端的第二数据速率输出第一数据组或第二数据组，而不切换测试模式。 第二数据速率可能低于第一数据速率。

公开(公告)号：US20080031055A1

公开(公告)日：2008-02-07

申请号：US11803454

申请日：2007-05-15

Applicant: Hyong-yong Lee

Inventor： Hyong-yong Lee

IPC: G11C29/00 ,  G11C7/10 ,  G11C7/00

CPC classification number: G11C29/14 ,  G11C7/22 ,  G11C7/222 ,  G11C29/12015

Abstract: A semiconductor memory device and a method for testing the same are capable of performing a low-frequency test operation even when a high-frequency external clock signal is input. The method for testing the semiconductor memory device comprises: interpreting a control command from a plurality of external control signals and generating a low-frequency operation control signal when an MRS command included in the control command designates a write and read test operation; when a write command is input as the control command, converting the write command into a low-frequency write command in response to the low-frequency operation control signal, generating an internal low-frequency clock signal in response to the low-frequency operation control signal, and performing a low-frequency write operation based on the internal low-frequency clock signal; and buffering an external clock signal to generate an internal normal-frequency clock signal and, when a read command is input as the control command, performing a read operation based on the internal normal-frequency clock signal in response to the read command.

Abstract translation: 半导体存储器件及其测试方法即使在输入高频外部时钟信号时也能执行低频测试操作。 用于测试半导体存储器件的方法包括：当包括在控制命令中的MRS命令指定写入和读取测试操作时，解释来自多个外部控制信号的控制命令并产生低频操作控制信号; 当写命令被输入作为控制命令时，响应于低频操作控制信号将写入命令转换成低频写入命令，响应于低频操作控制产生内部低频时钟信号 信号，并且基于内部低频时钟信号执行低频写入操作; 并且缓冲外部时钟信号以产生内部正常频率时钟信号，并且当输入读取命令作为控制命令时，响应于读取命令，基于内部正常频率时钟信号执行读取操作。

公开(公告)号：US07030635B2

公开(公告)日：2006-04-18

申请号：US10893341

申请日：2004-07-19

Applicant: Gwan-pyo Hong ,  Hyong-yong Lee

Inventor： Gwan-pyo Hong ,  Hyong-yong Lee

IPC: G01R31/02

CPC classification number: G01R25/00

Abstract: A device for measuring voltage, including a voltage detecting portion for detecting a plurality of voltages and outputting a maximum voltage of the plurality of voltages, a voltage latching portion that receives a first output from the voltage detecting portion, and a voltage reading portion that receives a second output from the voltage latching portion. Another device for measuring voltage, including a supply voltage, a ground voltage, and first and second supply voltage measuring units connected in parallel to each other between the supply voltage and the ground voltage. A method for measuring voltage, including receiving a plurality of voltages, detecting a maximum voltage from the plurality of voltages, maintaining the detected maximum voltage, and outputting the maintained detected maximum voltage.

Abstract translation: 一种用于测量电压的装置，包括用于检测多个电压并输出多个电压的最大电压的电压检测部分，接收来自电压检测部分的第一输出的电压锁存部分和接收电压检测部分的电压读取部分 来自电压锁存部分的第二输出。 用于测量电压的另一个装置，包括电源电压，接地电压以及在电源电压和接地电压之间并联连接的第一和第二电源电压测量单元。 一种用于测量电压的方法，包括接收多个电压，从多个电压检测最大电压，维持检测到的最大电压，并输出维持的检测到的最大电压。

公开(公告)号：US20050104611A1

公开(公告)日：2005-05-19

申请号：US10893341

申请日：2004-07-19

Applicant: Gwan-pyo Hong ,  Hyong-yong Lee

Inventor： Gwan-pyo Hong ,  Hyong-yong Lee

IPC: G01R31/26 ,  G01R19/165 ,  G01R25/00 ,  G01R31/30 ,  G11C5/14 ,  G01R31/02

CPC classification number: G01R25/00

Abstract: A device for measuring voltage, including a voltage detecting portion for detecting a plurality of voltages and outputting a maximum voltage of the plurality of voltages, a voltage latching portion that receives a first output from the voltage detecting portion, and a voltage reading portion that receives a second output from the voltage latching portion. Another device for measuring voltage, including a supply voltage, a ground voltage, and first and second supply voltage measuring units connected in parallel to each other between the supply voltage and the ground voltage. A method for measuring voltage, including receiving a plurality of voltages, detecting a maximum voltage from the plurality of voltages, maintaining the detected maximum voltage, and outputting the maintained detected maximum voltage.

Abstract translation: 一种用于测量电压的装置，包括用于检测多个电压并输出多个电压的最大电压的电压检测部分，接收来自电压检测部分的第一输出的电压锁存部分和接收电压检测部分的电压读取部分 来自电压锁存部分的第二输出。 用于测量电压的另一个装置，包括电源电压，接地电压以及在电源电压和接地电压之间并联连接的第一和第二电源电压测量单元。 一种用于测量电压的方法，包括接收多个电压，从多个电压检测最大电压，维持检测到的最大电压，并输出维持的检测到的最大电压。