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    Multi-level nonvolatile memory devices using variable resistive elements
    11.
    发明申请
    Multi-level nonvolatile memory devices using variable resistive elements 有权
    使用可变电阻元件的多级非易失性存储器件

    公开(公告)号：US20100208508A1

    公开(公告)日：2010-08-19

    申请号：US12656754

    申请日：2010-02-16

    Applicant: In-Gyu Baek ,  Hyun-Jun Sim ,  Hong-Sik Yoon ,  Jin-Shi Zhao ,  Min-Young Park

    Inventor： In-Gyu Baek ,  Hyun-Jun Sim ,  Hong-Sik Yoon ,  Jin-Shi Zhao ,  Min-Young Park

    IPC: G11C11/00

    CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2211/5641 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72

    Abstract: Multi-level nonvolatile memory devices using variable resistive elements, the multi-level nonvolatile memory devices including a word line, a bit line, and a multi-level memory cell coupled between the word line and the bit line, the multi-level memory cell having first resistance level and a second resistance level higher than the first resistance level when the first and second write biases having the same polarity are applied thereto, and a third resistance level and a fourth resistance level ranging between the first and second resistance levels, when third and fourth write biases having different polarities from each other are applied thereto.

    Abstract translation: 使用可变电阻元件的多级非易失性存储器件，多级非易失性存储器件包括字线，位线和耦合在字线和位线之间的多电平存储器单元，多电平存储器单元 当施加具有相同极性的第一和第二写入偏置时，具有高于第一电阻电平的第一电阻电平和第二电阻电平，以及在第一和第二电阻电平之间范围内的第三电阻电平和第四电阻电平，当 施加具有彼此不同极性的第三和第四写入偏置。

    Semiconductor memory device
    15.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08264018B2

    公开(公告)日：2012-09-11

    申请号：US12777683

    申请日：2010-05-11

    Applicant: Hong Sik Yoon ,  Jinshi Zhao ,  Ingyu Baek ,  Hyun Jun Sim ,  Minyoung Park

    Inventor： Hong Sik Yoon ,  Jinshi Zhao ,  Ingyu Baek ,  Hyun Jun Sim ,  Minyoung Park

    IPC: H01L29/80

    CPC classification number: H01L27/228 ,  H01L27/0207 ,  H01L27/2454 ,  H01L27/249

    Abstract: Provided is a semiconductor memory device. The semiconductor memory device may include a local bitline extending in a direction substantially vertical to an upper surface of a semiconductor substrate and a local wordline intersecting the local bitline. The local bitline is electrically connected to a bitline channel pillar penetrating a gate of a bitline transistor, and the local wordline is electrically connected to a wordline channel pillar penetrating a gate of a wordline transistor.

    Abstract translation: 提供了一种半导体存储器件。 半导体存储器件可以包括在基本上垂直于半导体衬底的上表面的方向上延伸的局部位线和与局部位线相交的局部字线。 局部位线电连接到贯穿位线晶体管的栅极的位线通道柱，并且本地字线电连接到贯穿字线晶体管的栅极的字线通道柱。

    Methods of Forming Resistive Memory Devices
    19.
    发明申请
    Methods of Forming Resistive Memory Devices 有权
    形成电阻式存储器件的方法

    公开(公告)号：US20100233849A1

    公开(公告)日：2010-09-16

    申请号：US12784230

    申请日：2010-05-20

    Applicant: Jang Eun Lee ,  Dae-Kyom Kim ,  Jun-Ho Jeong ,  Se-Chung Oh ,  Kyung-Tae Nam ,  Hyun-Jun Sim

    Inventor： Jang Eun Lee ,  Dae-Kyom Kim ,  Jun-Ho Jeong ,  Se-Chung Oh ,  Kyung-Tae Nam ,  Hyun-Jun Sim

    IPC: H01L21/36

    CPC classification number: H01L45/04 ,  H01L27/2418 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1633

    Abstract: Methods of forming a resistive memory device include forming an insulation layer on a semiconductor substrate including a conductive pattern, forming a contact hole in the insulation layer to expose the conductive pattern, forming a lower electrode in the contact hole, forming a variable resistive oxide layer in the contact hole on the lower electrode, forming a middle electrode in the contact hole on the variable resistive oxide layer, forming a buffer oxide layer on the middle electrode and the insulation layer, and forming an upper electrode on the buffer oxide layer. Related resistive memory devices are also disclosed.

    Abstract translation: 形成电阻性存储器件的方法包括在包括导电图案的半导体衬底上形成绝缘层，在绝缘层中形成接触孔以露出导电图案，在接触孔中形成下电极，形成可变电阻氧化物层 在下电极的接触孔中，在可变电阻氧化物层的接触孔中形成中间电极，在中间电极和绝缘层上形成缓冲氧化物层，在缓冲氧化物层上形成上电极。 还公开了相关的电阻式存储器件。

    Resistive memory devices and methods of forming resistive memory devices
    20.
    发明授权
    Resistive memory devices and methods of forming resistive memory devices 有权
    电阻式存储器件和形成电阻式存储器件的方法

    公开(公告)号：US07750336B2

    公开(公告)日：2010-07-06

    申请号：US12207889

    申请日：2008-09-10

    Applicant: Jang-Eun Lee ,  Dae-Kyom Kim ,  Jun-Ho Jeong ,  Se-Chung Oh ,  Kyung-Tae Nam ,  Hyun-Jun Sim

    Inventor： Jang-Eun Lee ,  Dae-Kyom Kim ,  Jun-Ho Jeong ,  Se-Chung Oh ,  Kyung-Tae Nam ,  Hyun-Jun Sim

    IPC: H01L47/00

    CPC classification number: H01L45/04 ,  H01L27/2418 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1633

    Abstract: Methods of forming a resistive memory device include forming an insulation layer on a semiconductor substrate including a conductive pattern, forming a contact hole in the insulation layer to expose the conductive pattern, forming a lower electrode in the contact hole, forming a variable resistive oxide layer in the contact hole on the lower electrode, forming a middle electrode in the contact hole on the variable resistive oxide layer, forming a buffer oxide layer on the middle electrode and the insulation layer, and forming an upper electrode on the buffer oxide layer. Related resistive memory devices are also disclosed.

    Abstract translation: 形成电阻性存储器件的方法包括在包括导电图案的半导体衬底上形成绝缘层，在绝缘层中形成接触孔以露出导电图案，在接触孔中形成下电极，形成可变电阻氧化物层 在下电极的接触孔中，在可变电阻氧化物层的接触孔中形成中间电极，在中间电极和绝缘层上形成缓冲氧化物层，在缓冲氧化物层上形成上电极。 还公开了相关的电阻式存储器件。

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