公开(公告)号：US20140220752A1

公开(公告)日：2014-08-07

申请号：US13799291

申请日：2013-03-13

Applicant: Jae-Young PARK ,  Ji-Hoon Cha ,  Jae-Jik Baek ,  Bon-Young Koo ,  Kang-Hun Moon ,  Bo-un Yoon

Inventor： Jae-Young PARK ,  Ji-Hoon Cha ,  Jae-Jik Baek ,  Bon-Young Koo ,  Kang-Hun Moon ,  Bo-un Yoon

IPC: H01L29/66

CPC classification number: H01L29/66795

Abstract: A method of fabricating a semiconductor device is described. The method of fabricating a semiconductor device comprises providing a fin formed to protrude from a substrate and a plurality of gate electrodes formed on the fin to intersect the fin; forming first recesses in the fin on at least one side of the respective gate electrodes; forming an oxide layer on the surfaces of the first recesses; and expanding the first recesses into second recesses by removing the oxide layer. Related devices are also disclosed.

Abstract translation: 描述制造半导体器件的方法。 制造半导体器件的方法包括提供形成为从基板突出的翅片和形成在鳍片上的与栅极相交的多个栅电极; 在所述翅片的至少一个侧面上形成第一凹部; 在所述第一凹部的表面上形成氧化物层; 并且通过去除氧化物层将第一凹槽膨胀成第二凹陷。 还公开了相关设备。

公开(公告)号：US20120142159A1

公开(公告)日：2012-06-07

申请号：US13242302

申请日：2011-09-23

Applicant: Tae-Gon Kim ,  Sang-Bom Kang ,  Jae-Young Park ,  Kang-Hun Moon ,  Hyun-Jun Sim ,  Seung-Hun Lee ,  Han-Ki Lee ,  Hyun-Seung Kim

Inventor： Tae-Gon Kim ,  Sang-Bom Kang ,  Jae-Young Park ,  Kang-Hun Moon ,  Hyun-Jun Sim ,  Seung-Hun Lee ,  Han-Ki Lee ,  Hyun-Seung Kim

IPC: H01L21/336 ,  H01L21/20

CPC classification number: H01L21/26586 ,  H01L21/2257 ,  H01L21/26513 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: Methods for fabricating a semiconductor device are provided wherein, in an embodiment, the method includes the steps of forming a gate electrode on a semiconductor substrate, forming a trench by recessing the semiconductor substrate in the vicinity of the gate electrode, doping an anti-diffusion ion into a portion of the semiconductor substrate in the trench, and growing an impurity-doped epitaxial layer on the semiconductor substrate doped with the anti-diffusion ion.

Abstract translation: 提供了制造半导体器件的方法，其中在一个实施例中，该方法包括以下步骤：在半导体衬底上形成栅电极，通过在栅极附近凹入半导体衬底形成沟槽，掺杂抗扩散 离子进入沟槽中的半导体衬底的一部分，并且在掺杂有抗扩散离子的半导体衬底上生长杂质掺杂的外延层。

公开(公告)号：US20160293717A1

公开(公告)日：2016-10-06

申请号：US14990793

申请日：2016-01-08

Applicant: Jin Bum KIM ,  Chul Sung KIM ,  Kang Hun MOON ,  Yang XU ,  Bon Young KOO

Inventor： Jin Bum KIM ,  Chul Sung KIM ,  Kang Hun MOON ,  Yang XU ,  Bon Young KOO

IPC: H01L29/417 ,  H01L27/088 ,  H01L27/11 ,  H01L29/161 ,  H01L29/36 ,  H01L29/45 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/41791 ,  H01L27/1104 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/36 ,  H01L29/41758 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: A semiconductor device includes a substrate having an upper surface, a plurality of active fins on the substrate, a gate electrode crossing the plurality of active fins, and at each side of the gate electrode, a source/drain region on the plurality of active fins. The source/drain region may include a plurality of first regions extending from the active fins, and a second region between each of the plurality of first regions. The second region may have a second germanium concentration greater than the first germanium concentration. The source/drain region may be connected to a contact plug, and may have a top surface that has a wave shaped, or curved surface. The top surface may have a larger surface area than a top surface of the contact plug.

Abstract translation: 半导体器件包括具有上表面的衬底，衬底上的多个有源散热片，与多个有源散热片交叉的栅电极，以及在栅电极的每一侧上的多个活动鳍片上的源极/漏极区域 。 源极/漏极区域可以包括从活性鳍片延伸的多个第一区域，以及在多个第一区域中的每一个之间的第二区域。 第二区域可具有大于第一锗浓度的第二锗浓度。 源极/漏极区域可以连接到接触插塞，并且可以具有具有波形或曲面的顶表面。 顶表面可以具有比接触插塞顶表面更大的表面积。

公开(公告)号：US08759182B2

公开(公告)日：2014-06-24

申请号：US13459740

申请日：2012-04-30

Applicant: Hyun-Jun Sim ,  Jae-Young Park ,  Hyun-Seung Kim ,  Sang-Bom Kang ,  Sun-Ghil Lee ,  Hyun-Deok Yang ,  Kang-Hun Moon ,  Han-Ki Lee ,  Sang-Mi Choi

Inventor： Hyun-Jun Sim ,  Jae-Young Park ,  Hyun-Seung Kim ,  Sang-Bom Kang ,  Sun-Ghil Lee ,  Hyun-Deok Yang ,  Kang-Hun Moon ,  Han-Ki Lee ,  Sang-Mi Choi

IPC: H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/28185 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7833

Abstract: A semiconductor device having an improved negative bias temperature instability lifetime characteristic is manufactured by forming a first insulating layer on a substrate, performing a first nitridation on the first insulating layer to form a second insulating layer, and sequentially performing a first and second anneal on the second insulating layer to form a third insulating layer, wherein the second anneal is performed at a higher temperature and with a different gas than the first anneal. A second nitridation is performed on the third insulating layer to form a fourth insulating layer, and a sequential third and fourth anneal on the fourth insulating layer forms a fifth insulating layer. The third anneal is performed at a higher temperature than the first anneal, and the fourth anneal is performed at a higher temperature than the second anneal and with a different gas than the third anneal.

Abstract translation: 通过在基板上形成第一绝缘层，在第一绝缘层上进行第一次氮化，形成第二绝缘层，依次进行第一和第二退火，制造具有改善的负偏压温度不稳定寿命特性的半导体器件 第二绝缘层以形成第三绝缘层，其中所述第二退火在比所述第一退火更高的温度和不同的气体下进行。 在第三绝缘层上进行第二次氮化，以形成第四绝缘层，并且在第四绝缘层上顺序的第三和第四退火形成第五绝缘层。 第三退火在比第一退火更高的温度下进行，第四退火在比第二退火更高的温度下进行，并且具有比第三退火不同的气体。

公开(公告)号：US20120299154A1

公开(公告)日：2012-11-29

申请号：US13459740

申请日：2012-04-30

Applicant: Hyun-Jun Sim ,  Jae-Young Park ,  Hyun-Seung Kim ,  Sang-Bom Kang ,  Sun-Ghil Lee ,  Hyun-Deok Yang ,  Kang-Hun Moon ,  Han-Ki Lee ,  Sang-Mi Choi

Inventor： Hyun-Jun Sim ,  Jae-Young Park ,  Hyun-Seung Kim ,  Sang-Bom Kang ,  Sun-Ghil Lee ,  Hyun-Deok Yang ,  Kang-Hun Moon ,  Han-Ki Lee ,  Sang-Mi Choi

IPC: H01L29/00 ,  H01L21/336 ,  H01L21/04

CPC classification number: H01L29/6659 ,  H01L21/28185 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7833

Abstract: A semiconductor device having an improved negative bias temperature instability lifetime characteristic is manufactured by forming a first insulating layer on a substrate, performing a first nitridation on the first insulating layer to form a second insulating layer, and sequentially performing a first and second anneal on the second insulating layer to form a third insulating layer, wherein the second anneal is performed at a higher temperature and with a different gas than the first anneal. A second nitridation is performed on the third insulating layer to form a fourth insulating layer, and a sequential third and fourth anneal on the fourth insulating layer forms a fifth insulating layer. The third anneal is performed at a higher temperature than the first anneal, and the fourth anneal is performed at a higher temperature than the second anneal and with a different gas than the third anneal.

Abstract translation: 通过在基板上形成第一绝缘层，在第一绝缘层上进行第一次氮化，形成第二绝缘层，依次进行第一和第二退火，制造具有改善的负偏压温度不稳定寿命特性的半导体器件 第二绝缘层以形成第三绝缘层，其中所述第二退火在比所述第一退火更高的温度和不同的气体下进行。 在第三绝缘层上进行第二次氮化，以形成第四绝缘层，并且在第四绝缘层上顺序的第三和第四退火形成第五绝缘层。 第三退火在比第一退火更高的温度下进行，第四退火在比第二退火更高的温度下进行，并且具有比第三退火不同的气体。

公开(公告)号：US20120269498A1

公开(公告)日：2012-10-25

申请号：US13452052

申请日：2012-04-20

Applicant: Gonsu KANG ,  Sangbom KANG ,  Jaeyoung PARK ,  Sungho KANG ,  Taegon KIM ,  Hyunsub EARM ,  Jong-hoon KANG ,  Kang Hun MOON ,  Han Ki LEE

Inventor： Gonsu KANG ,  Sangbom KANG ,  Jaeyoung PARK ,  Sungho KANG ,  Taegon KIM ,  Hyunsub EARM ,  Jong-hoon KANG ,  Kang Hun MOON ,  Han Ki LEE

IPC: F27D5/00 ,  F26B3/30

CPC classification number: F27B17/0025 ,  H01L21/67115 ,  H01L21/6875

Abstract: A substrate treatment apparatus and a supporting unit are provided. The substrate treatment apparatus includes a chamber in which a substrate is processed; a supporting unit that is disposed in the chamber and is configured to support the substrate; and a heating member that is configured to apply heat to the substrate supported by the supporting unit. The supporting unit includes a plate; a plurality of supporting pins upwardly protruding from the plate; and at least one auxiliary pin upwardly protruding from the plate. A distance between a central point of the plate and the at least one auxiliary pin is different from a distance between the central point of the plate and the supporting pins.

Abstract translation: 提供了基板处理装置和支撑单元。 基板处理装置包括：处理基板的室; 支撑单元，其设置在所述室中并且构造成支撑所述基板; 以及加热构件，其构造成对由所述支撑单元支撑的所述基板施加热量。 支撑单元包括板; 从所述板向上突出的多个支撑销; 以及从板向上突出的至少一个辅助销。 板的中心点和至少一个辅助销之间的距离不同于板的中心点和支撑销之间的距离。

公开(公告)号：US09461148B2

公开(公告)日：2016-10-04

申请号：US13799291

申请日：2013-03-13

Applicant: Jae-Young Park ,  Ji-Hoon Cha ,  Jae-Jik Baek ,  Bon-Young Koo ,  Kang-Hun Moon ,  Bo-Un Yoon

Inventor： Jae-Young Park ,  Ji-Hoon Cha ,  Jae-Jik Baek ,  Bon-Young Koo ,  Kang-Hun Moon ,  Bo-Un Yoon

IPC: H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/66795

Abstract: A method of fabricating a semiconductor device is described. The method of fabricating a semiconductor device comprises providing a fin formed to protrude from a substrate and a plurality of gate electrodes formed on the fin to intersect the fin; forming first recesses in the fin on at least one side of the respective gate electrodes; forming an oxide layer on the surfaces of the first recesses; and expanding the first recesses into second recesses by removing the oxide layer. Related devices are also disclosed.

Abstract translation: 描述制造半导体器件的方法。 制造半导体器件的方法包括提供形成为从基板突出的翅片和形成在鳍片上的与栅极相交的多个栅电极; 在所述翅片的至少一个侧面上形成第一凹部; 在所述第一凹部的表面上形成氧化物层; 并且通过去除氧化物层将第一凹槽膨胀成第二凹陷。 还公开了相关设备。