公开(公告)号：US08358527B2

公开(公告)日：2013-01-22

申请号：US12656754

申请日：2010-02-16

Applicant: In-Gyu Baek ,  Hyun-Jun Sim ,  Hong-Sik Yoon ,  Jin-Shi Zhao ,  Min-Young Park

Inventor： In-Gyu Baek ,  Hyun-Jun Sim ,  Hong-Sik Yoon ,  Jin-Shi Zhao ,  Min-Young Park

IPC: G11C11/00 ,  H01L47/00

CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2211/5641 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72

Abstract: Multi-level nonvolatile memory devices using variable resistive elements, the multi-level nonvolatile memory devices including a word line, a bit line, and a multi-level memory cell coupled between the word line and the bit line, the multi-level memory cell having first resistance level and a second resistance level higher than the first resistance level when the first and second write biases having the same polarity are applied thereto, and a third resistance level and a fourth resistance level ranging between the first and second resistance levels, when third and fourth write biases having different polarities from each other are applied thereto.

Abstract translation: 使用可变电阻元件的多级非易失性存储器件，多级非易失性存储器件包括字线，位线和耦合在字线和位线之间的多电平存储器单元，多电平存储器单元 当施加具有相同极性的第一和第二写入偏置时，具有高于第一电阻电平的第一电阻电平和第二电阻电平，以及在第一和第二电阻电平之间范围内的第三电阻电平和第四电阻电平，当 施加具有彼此不同极性的第三和第四写入偏置。

公开(公告)号：US08058097B2

公开(公告)日：2011-11-15

申请号：US12784230

申请日：2010-05-20

Applicant: Jang-Eun Lee ,  Dae-Kyom Kim ,  Jun-Ho Jeong ,  Se-Chung Oh ,  Kyung-Tae Nam ,  Hyun-Jun Sim

Inventor： Jang-Eun Lee ,  Dae-Kyom Kim ,  Jun-Ho Jeong ,  Se-Chung Oh ,  Kyung-Tae Nam ,  Hyun-Jun Sim

IPC: H01L21/36

CPC classification number: H01L45/04 ,  H01L27/2418 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1633

Abstract: Methods of forming a resistive memory device include forming an insulation layer on a semiconductor substrate including a conductive pattern, forming a contact hole in the insulation layer to expose the conductive pattern, forming a lower electrode in the contact hole, forming a variable resistive oxide layer in the contact hole on the lower electrode, forming a middle electrode in the contact hole on the variable resistive oxide layer, forming a buffer oxide layer on the middle electrode and the insulation layer, and forming an upper electrode on the buffer oxide layer. Related resistive memory devices are also disclosed.

Abstract translation: 形成电阻性存储器件的方法包括在包括导电图案的半导体衬底上形成绝缘层，在绝缘层中形成接触孔以露出导电图案，在接触孔中形成下电极，形成可变电阻氧化物层 在下电极的接触孔中，在可变电阻氧化物层的接触孔中形成中间电极，在中间电极和绝缘层上形成缓冲氧化物层，在缓冲氧化物层上形成上电极。 还公开了相关的电阻式存储器件。

公开(公告)号：US20100289084A1

公开(公告)日：2010-11-18

申请号：US12777683

申请日：2010-05-11

Applicant: Hong Sik Yoon ,  Jinshi Zhao ,  Ingyu Baek ,  Hyun Jun Sim ,  Minyoung Park

Inventor： Hong Sik Yoon ,  Jinshi Zhao ,  Ingyu Baek ,  Hyun Jun Sim ,  Minyoung Park

IPC: H01L29/78

CPC classification number: H01L27/228 ,  H01L27/0207 ,  H01L27/2454 ,  H01L27/249

Abstract: Provided is a semiconductor memory device. The semiconductor memory device may include a local bitline extending in a direction substantially vertical to an upper surface of a semiconductor substrate and a local wordline intersecting the local bitline. The local bitline is electrically connected to a bitline channel pillar penetrating a gate of a bitline transistor, and the local wordline is electrically connected to a wordline channel pillar penetrating a gate of a wordline transistor.

Abstract translation: 提供了一种半导体存储器件。 半导体存储器件可以包括在基本上垂直于半导体衬底的上表面的方向上延伸的局部位线和与局部位线相交的局部字线。 局部位线电连接到贯穿位线晶体管的栅极的位线通道柱，并且本地字线电连接到贯穿字线晶体管的栅极的字线通道柱。

公开(公告)号：US20090065760A1

公开(公告)日：2009-03-12

申请号：US12207889

申请日：2008-09-10

Applicant: Jang Eun Lee ,  Dae-Kyom Kim ,  Jun-Ho Jeong ,  Se-Chung Oh ,  Kyung-Tae Nam ,  Hyun-Jun Sim

Inventor： Jang Eun Lee ,  Dae-Kyom Kim ,  Jun-Ho Jeong ,  Se-Chung Oh ,  Kyung-Tae Nam ,  Hyun-Jun Sim

IPC: H01L45/00 ,  H01L21/44

CPC classification number: H01L45/04 ,  H01L27/2418 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1633

Abstract: Methods of forming a resistive memory device include forming an insulation layer on a semiconductor substrate including a conductive pattern, forming a contact hole in the insulation layer to expose the conductive pattern, forming a lower electrode in the contact hole, forming a variable resistive oxide layer in the contact hole on the lower electrode, forming a middle electrode in the contact hole on the variable resistive oxide layer, forming a buffer oxide layer on the middle electrode and the insulation layer, and forming an upper electrode on the buffer oxide layer. Related resistive memory devices are also disclosed.

Abstract translation: 形成电阻性存储器件的方法包括在包括导电图案的半导体衬底上形成绝缘层，在绝缘层中形成接触孔以露出导电图案，在接触孔中形成下电极，形成可变电阻氧化物层 在下电极的接触孔中，在可变电阻氧化物层的接触孔中形成中间电极，在中间电极和绝缘层上形成缓冲氧化物层，在缓冲氧化物层上形成上电极。 还公开了相关的电阻式存储器件。

公开(公告)号：US20120299154A1

公开(公告)日：2012-11-29

申请号：US13459740

申请日：2012-04-30

Applicant: Hyun-Jun Sim ,  Jae-Young Park ,  Hyun-Seung Kim ,  Sang-Bom Kang ,  Sun-Ghil Lee ,  Hyun-Deok Yang ,  Kang-Hun Moon ,  Han-Ki Lee ,  Sang-Mi Choi

Inventor： Hyun-Jun Sim ,  Jae-Young Park ,  Hyun-Seung Kim ,  Sang-Bom Kang ,  Sun-Ghil Lee ,  Hyun-Deok Yang ,  Kang-Hun Moon ,  Han-Ki Lee ,  Sang-Mi Choi

IPC: H01L29/00 ,  H01L21/336 ,  H01L21/04

CPC classification number: H01L29/6659 ,  H01L21/28185 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7833

Abstract: A semiconductor device having an improved negative bias temperature instability lifetime characteristic is manufactured by forming a first insulating layer on a substrate, performing a first nitridation on the first insulating layer to form a second insulating layer, and sequentially performing a first and second anneal on the second insulating layer to form a third insulating layer, wherein the second anneal is performed at a higher temperature and with a different gas than the first anneal. A second nitridation is performed on the third insulating layer to form a fourth insulating layer, and a sequential third and fourth anneal on the fourth insulating layer forms a fifth insulating layer. The third anneal is performed at a higher temperature than the first anneal, and the fourth anneal is performed at a higher temperature than the second anneal and with a different gas than the third anneal.

Abstract translation: 通过在基板上形成第一绝缘层，在第一绝缘层上进行第一次氮化，形成第二绝缘层，依次进行第一和第二退火，制造具有改善的负偏压温度不稳定寿命特性的半导体器件 第二绝缘层以形成第三绝缘层，其中所述第二退火在比所述第一退火更高的温度和不同的气体下进行。 在第三绝缘层上进行第二次氮化，以形成第四绝缘层，并且在第四绝缘层上顺序的第三和第四退火形成第五绝缘层。 第三退火在比第一退火更高的温度下进行，第四退火在比第二退火更高的温度下进行，并且具有比第三退火不同的气体。

公开(公告)号：US08314003B2

公开(公告)日：2012-11-20

申请号：US13101263

申请日：2011-05-05

Applicant: In-Gyu Baek ,  Hyun-Jun Sim ,  Jin-Shi Zhao ,  Eun-Kyung Yim

Inventor： In-Gyu Baek ,  Hyun-Jun Sim ,  Jin-Shi Zhao ,  Eun-Kyung Yim

IPC: H01L21/20

CPC classification number: G11C13/0007 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/003 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1633

Abstract: A nonvolatile memory device, a method of fabricating the nonvolatile memory device and a processing system including the nonvolatile memory device. The nonvolatile memory device may include a plurality of internal electrodes that extend in a direction substantially perpendicular to a face of a substrate, a plurality of first external electrodes that extend substantially in parallel with the face of the substrate, and a plurality of second external electrodes that also extend substantially in parallel with the face of the substrate. Each first external electrode is on a first side of a respective one of the internal electrodes, and each second external electrode is on a second side of a respective one of the internal electrodes. These devices also include a plurality of variable resistors that contact the internal electrodes, the first external electrodes and the second external electrodes.

Abstract translation: 非易失性存储器件，非易失性存储器件的制造方法和包括非易失性存储器件的处理系统。 非易失性存储装置可以包括沿基板垂直于基板的方向延伸的多个内部电极，基本上平行于基板的表面延伸的多个第一外部电极和多个第二外部电极 其也基本上平行于衬底的表面延伸。 每个第一外部电极在相应的一个内部电极的第一侧上，并且每个第二外部电极在相应的一个内部电极的第二侧上。 这些器件还包括接触内部电极，第一外部电极和第二外部电极的多个可变电阻器。

公开(公告)号：US07867902B2

公开(公告)日：2011-01-11

申请号：US12499832

申请日：2009-07-09

Applicant: Suk-Hun Choi ,  Chang-Ki Hong ,  Hyun-Jun Sim ,  Yoon-Ho Son

Inventor： Suk-Hun Choi ,  Chang-Ki Hong ,  Hyun-Jun Sim ,  Yoon-Ho Son

IPC: H01L21/44 ,  H01L21/311 ,  H01L21/4763

CPC classification number: H01L21/7684 ,  H01L21/28273 ,  H01L21/76802 ,  H01L21/76844 ,  H01L21/76885 ,  H01L23/485 ,  H01L23/53257 ,  H01L27/11541 ,  H01L27/11548 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of forming a contact structure, a first insulation layer including a first contact hole is formed on a substrate. A metal layer including tungsten is formed to fill the first contact hole. A planarization process is performed on the metal layer until the first insulation layer is exposed to form a first contact. A second contact is grown from the first contact. The second contact is formed without performing a photolithography process and an etching process to prevent misalignments.

Abstract translation: 在形成接触结构的方法中，在基板上形成包括第一接触孔的第一绝缘层。 形成包括钨的金属层以填充第一接触孔。 在金属层上进行平坦化处理，直到暴露第一​​绝缘层以形成第一接触。 从第一个联系人生长第二个联系人。 形成第二接触，而不进行光刻工艺和蚀刻工艺以防止未对准。

公开(公告)号：US20090230512A1

公开(公告)日：2009-09-17

申请号：US12353553

申请日：2009-01-14

Applicant: In-Gyu Baek ,  Hyun-Jun Sim ,  Jin-Shi Zhao ,  Eun-Kyung Yim

Inventor： In-Gyu Baek ,  Hyun-Jun Sim ,  Jin-Shi Zhao ,  Eun-Kyung Yim

IPC: H01L29/00

CPC classification number: G11C13/0007 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/003 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1633

Abstract: A nonvolatile memory device, a method of fabricating the nonvolatile memory device and a processing system including the nonvolatile memory device. The nonvolatile memory device may include a plurality of internal electrodes that extend in a direction substantially perpendicular to a face of a substrate, a plurality of first external electrodes that extend substantially in parallel with the face of the substrate, and a plurality of second external electrodes that also extend substantially in parallel with the face of the substrate. Each first external electrode is on a first side of a respective one of the internal electrodes, and each second external electrode is on a second side of a respective one of the internal electrodes. These devices also include a plurality of variable resistors that contact the internal electrodes, the first external electrodes and the second external electrodes.

Abstract translation: 非易失性存储器件，非易失性存储器件的制造方法和包括非易失性存储器件的处理系统。 非易失性存储装置可以包括沿基板垂直于基板的方向延伸的多个内部电极，基本上平行于基板的表面延伸的多个第一外部电极和多个第二外部电极 其也基本上平行于衬底的表面延伸。 每个第一外部电极在相应的一个内部电极的第一侧上，并且每个第二外部电极在相应的一个内部电极的第二侧上。 这些器件还包括接触内部电极，第一外部电极和第二外部电极的多个可变电阻器。

公开(公告)号：US08759182B2

公开(公告)日：2014-06-24

申请号：US13459740

申请日：2012-04-30

Applicant: Hyun-Jun Sim ,  Jae-Young Park ,  Hyun-Seung Kim ,  Sang-Bom Kang ,  Sun-Ghil Lee ,  Hyun-Deok Yang ,  Kang-Hun Moon ,  Han-Ki Lee ,  Sang-Mi Choi

Inventor： Hyun-Jun Sim ,  Jae-Young Park ,  Hyun-Seung Kim ,  Sang-Bom Kang ,  Sun-Ghil Lee ,  Hyun-Deok Yang ,  Kang-Hun Moon ,  Han-Ki Lee ,  Sang-Mi Choi

IPC: H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/28185 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7833

Abstract: A semiconductor device having an improved negative bias temperature instability lifetime characteristic is manufactured by forming a first insulating layer on a substrate, performing a first nitridation on the first insulating layer to form a second insulating layer, and sequentially performing a first and second anneal on the second insulating layer to form a third insulating layer, wherein the second anneal is performed at a higher temperature and with a different gas than the first anneal. A second nitridation is performed on the third insulating layer to form a fourth insulating layer, and a sequential third and fourth anneal on the fourth insulating layer forms a fifth insulating layer. The third anneal is performed at a higher temperature than the first anneal, and the fourth anneal is performed at a higher temperature than the second anneal and with a different gas than the third anneal.

Abstract translation: 通过在基板上形成第一绝缘层，在第一绝缘层上进行第一次氮化，形成第二绝缘层，依次进行第一和第二退火，制造具有改善的负偏压温度不稳定寿命特性的半导体器件 第二绝缘层以形成第三绝缘层，其中所述第二退火在比所述第一退火更高的温度和不同的气体下进行。 在第三绝缘层上进行第二次氮化，以形成第四绝缘层，并且在第四绝缘层上顺序的第三和第四退火形成第五绝缘层。 第三退火在比第一退火更高的温度下进行，第四退火在比第二退火更高的温度下进行，并且具有比第三退火不同的气体。

公开(公告)号：US20110204315A1

公开(公告)日：2011-08-25

申请号：US13101263

申请日：2011-05-05

Applicant: In-Gyu Baek ,  Hyun-Jun Sim ,  Jin-Shi Zhao ,  Eun-Kyung Yim

Inventor： In-Gyu Baek ,  Hyun-Jun Sim ,  Jin-Shi Zhao ,  Eun-Kyung Yim

IPC: H01L45/00 ,  H01L21/8239

CPC classification number: G11C13/0007 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/003 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1633

Abstract: A nonvolatile memory device, a method of fabricating the nonvolatile memory device and a processing system including the nonvolatile memory device. The nonvolatile memory device may include a plurality of internal electrodes that extend in a direction substantially perpendicular to a face of a substrate, a plurality of first external electrodes that extend substantially in parallel with the face of the substrate, and a plurality of second external electrodes that also extend substantially in parallel with the face of the substrate. Each first external electrode is on a first side of a respective one of the internal electrodes, and each second external electrode is on a second side of a respective one of the internal electrodes. These devices also include a plurality of variable resistors that contact the internal electrodes, the first external electrodes and the second external electrodes.

Abstract translation: 非易失性存储器件，非易失性存储器件的制造方法和包括非易失性存储器件的处理系统。 非易失性存储装置可以包括沿基板垂直于基板的方向延伸的多个内部电极，基本上平行于基板的表面延伸的多个第一外部电极和多个第二外部电极 其也基本上平行于衬底的表面延伸。 每个第一外部电极在相应的一个内部电极的第一侧上，并且每个第二外部电极在相应的一个内部电极的第二侧上。 这些器件还包括接触内部电极，第一外部电极和第二外部电极的多个可变电阻器。