公开(公告)号：US20050114064A1

公开(公告)日：2005-05-26

申请号：US10911503

申请日：2004-08-05

Applicant: Joo-weon Shin ,  Byung-chul Kim ,  Seung-bum Ko ,  Soo-in Cho

Inventor： Joo-weon Shin ,  Byung-chul Kim ,  Seung-bum Ko ,  Soo-in Cho

IPC: G11C29/00 ,  G01D3/00 ,  G11C29/34

CPC classification number: G11C29/34 ,  G11C2029/2602

Abstract: A method for performing a parallel bit test of a semiconductor memory device, including writing data to each of a plurality of memory cells, reading data from each of the plurality of memory cells, testing the data from each of the plurality of memory cells in a first test mode, and testing the data from each of the plurality of memory cells in a second test mode. A circuit including a first test mode circuit for receiving first data, a second test mode circuit for receiving second data, and wherein the first test mode circuit tests the received first data and the second test mode tests the received second data. Another circuit including a first comparator with a plurality of comparison circuits, a test mode selector for selecting at least one of a plurality of outputs from the first comparator, and a second comparator for receiving the selected output.

Abstract translation: 一种用于执行半导体存储器件的并行位测试的方法，包括将数据写入多个存储器单元中的每一个，从多个存储器单元中的每一个读取数据，在多个存储单元中的每一个存储单元中测试数据 第一测试模式，并且在第二测试模式中测试来自多个存储器单元中的每一个的数据。 一种电路，包括用于接收第一数据的第一测试模式电路，用于接收第二数据的第二测试模式电路，并且其中第一测试模式电路测试接收的第一数据，第二测试模式测试接收的第二数据。 另一个电路包括具有多个比较电路的第一比较器，用于选择来自第一比较器的多个输出中的至少一个的测试模式选择器，以及用于接收所选输出的第二比较器。

公开(公告)号：US20050089276A1

公开(公告)日：2005-04-28

申请号：US10883529

申请日：2004-06-30

Applicant: Keun Yoon ,  In Cho ,  Seung Ahn ,  Myung Jeong

Inventor： Keun Yoon ,  In Cho ,  Seung Ahn ,  Myung Jeong

IPC: G02B6/12 ,  G02B6/42 ,  G02B6/43 ,  H05K1/02 ,  G02B6/26

CPC classification number: G02B6/43 ,  G02B6/42 ,  H01L2224/48091 ,  H05K1/0274 ,  H01L2924/00014

Abstract: An optical printed circuit board system having a tapered optical waveguide is provided. The optical printed circuit board system includes a substrate as a printed circuit board having an electrical circuit and on which an electrical circuit chip is mounted, a system board including an optical bench coupled to the substrate and on which a photoelectrical signal chip electrically connected to the electrical circuit chip through the electrical circuit, an optical device electrically connected to the photoelectrical signal chip, and a first optical waveguide aligned to the optical device for optical coupling and tapered to have a smaller aperture in an output node for outputting the optical signals smaller than that in an input node for inputting the optical signals are mounted, and a back plane including a groove into which the system board is inserted and a second optical waveguide optically coupled to the first optical waveguide and tapered to have a smaller aperture in the output node than in the input node. The input node of the first optical waveguide is optically coupled to the output node of the second optical waveguide or the output node of the first optical waveguide is optically coupled to the input node of the second optical waveguide.

Abstract translation: 提供了一种具有锥形光波导的光学印刷电路板系统。 光学印刷电路板系统包括具有电路并且其上安装有电路芯片的印刷电路板的基板，系统板，其包括耦合到基板的光学台，并且光电信号芯片电连接到基板 通过电路的电路芯片，与光电信号芯片电连接的光学器件，以及与光耦合的光学器件对准的第一光波导，并且在输出节点中具有较小的孔径，用于输出小于 在用于输入光信号的输入节点中安装用于输入光信号的输入节点和包括凹槽的背面，其中插入系统板，并且第二光波导光学耦合到第一光波导并且在输出节点中具有较小的孔径 比在输入节点。 第一光波导的输入节点光耦合到第二光波导的输出节点，或者第一光波导的输出节点光耦合到第二光波导的输入节点。

公开(公告)号：US20050009490A1

公开(公告)日：2005-01-13

申请号：US10841591

申请日：2004-05-06

Applicant: Hyung-Soo Lee ,  Sang-In Cho ,  Kyu-Min Kang ,  Chang-Joo Kim

Inventor： Hyung-Soo Lee ,  Sang-In Cho ,  Kyu-Min Kang ,  Chang-Joo Kim

IPC: H04B7/26 ,  H03G3/30 ,  H04B1/69 ,  H04B7/005 ,  H03F3/45

CPC classification number: H04W52/52 ,  H03G3/3052 ,  H03G2201/103 ,  H03G2201/502 ,  H03G2201/702 ,  H04B1/71637

Abstract: Disclosed is a method for controlling power level of received signal in an ultra wide band transmission system which uses multi frequency bands, and includes a pre-gain controller (PGC) and a voltage gain amplifier (VGA). The method for controlling a power level of a received signal includes the steps of: a) at the PGCs, detecting which multi frequency band is used in a transmitter of the transmission system; b) at the PGCs, obtaining the voltage gain owing to the discrepancy in the power levels of the received signals; and c) at the PGCs, compensating for the power loss based on the voltage gain.

Abstract translation: 公开了一种在使用多频带的超宽带传输系统中控制接收信号的功率电平的方法，包括预增益控制器（PGC）和电压增益放大器（VGA）。 用于控制接收信号的功率电平的方法包括以下步骤：a）在PGC检测在传输系统的发射机中使用哪个多频带; b）在PGC处，由于接收到的信号的功率电平的差异而获得电压增益; 和c）在PGC处，基于电压增益来补偿功率损耗。

公开(公告)号：US20050000544A1

公开(公告)日：2005-01-06

申请号：US10868834

申请日：2004-06-17

Applicant: In Cho ,  Joung Kim

Inventor： In Cho ,  Joung Kim

IPC: D06F39/00 ,  B08B13/00

CPC classification number: A47L15/0021 ,  A47L15/0049 ,  A47L15/4297 ,  A47L2401/10 ,  A47L2401/30 ,  A47L2501/01 ,  A47L2501/02 ,  A47L2501/26 ,  A47L2501/30

Abstract: A dishwasher and a method for controlling the same, performing a main washing cycle depending upon an amount of food residue on used dishes or a pollution level thereof, are disclosed. The method includes supplying washing water to the dishwasher, detecting for an N number of times a pollution level of the supplied washing water during a preliminary washing cycle, and comparing the detected pollution levels with a reference pollution level, and carrying out a main washing cycle depending upon a comparison result between the detected pollution levels and the reference pollution level.

Abstract translation: 公开了一种洗碗机及其控制方法，其特征在于，根据所使用的餐盘上的食物残留量或其污染程度进行主洗涤循环。 该方法包括向洗碗机供给洗涤水，在初步洗涤循环期间检测N次污染水平的污染水平，并将检测到的污染水平与参考污染水平进行比较，并执行主洗涤循环 取决于检测到的污染水平与参考污染水平之间的比较结果。

公开(公告)号：US6094376A

公开(公告)日：2000-07-25

申请号：US998287

申请日：1997-12-24

Applicant: Pil-Soon Park ,  Kyung-Woo Kang ,  Soo-In Cho

Inventor： Pil-Soon Park ,  Kyung-Woo Kang ,  Soo-In Cho

IPC: G11C11/417 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C16/04

CPC classification number: G11C7/1051

Abstract: A data output buffer control circuit for a semiconductor memory device assures a column address setup time and a valid data setup time in EDO mode by eliminating short glitches in the data output buffer. The circuit assures the column address setup time by disabling the data output buffer for a predetermined period of time after an address transition, regardless of the state of a column address strobe signal. The circuit assures the setup time for valid data by sensing when the address is set up relative to when the column address strobe signal is activated, and then enabling the data output buffer so as to maintain invalid data in the data output buffer long enough to prevent a short glitch in the data output buffer if the column address is set up before the column address strobe signal is activated. The circuit includes a pulse generator for generating a pulse signal each time it senses a column address transition, and a latch circuit for combining the pulse signal with the column address strobe signal so as to generate a buffer control signal for enabling and disabling the data output buffer.

Abstract translation: 用于半导体存储器件的数据输出缓冲器控制电路通过消除数据输出缓冲器中的短毛刺来确保EDO模式下的列地址建立时间和有效的数据建立时间。 该电路通过在地址转换之后的预定时间段禁用数据输出缓冲器来确保列地址建立时间，而不管列地址选通信号的状态如何。 电路通过检测地址是否相对于列地址选通信号被激活而设置的时间来保证有效数据的建立时间，然后启用数据输出缓冲器，以便在数据输出缓冲器中保持足够长的时间以防止 如果在列地址选通信号被激活之前设置了列地址，则数据输出缓冲器中的短暂毛刺。 电路包括用于每次检测列地址转换时产生脉冲信号的脉冲发生器和用于将脉冲信号与列地址选通信号组合的锁存电路，以便产生用于启用和禁用数据输出的缓冲器控制信号 缓冲。

公开(公告)号：US5610869A

公开(公告)日：1997-03-11

申请号：US511815

申请日：1995-08-07

Applicant: Seung-Moon Yoo ,  Ejaz ul Haq ,  Yun-Ho Choi ,  Soo-In Cho ,  Dae-Je Chin ,  Nam-Soo Kang ,  Seung-Hun Lee

Inventor： Seung-Moon Yoo ,  Ejaz ul Haq ,  Yun-Ho Choi ,  Soo-In Cho ,  Dae-Je Chin ,  Nam-Soo Kang ,  Seung-Hun Lee

IPC: G11C5/14 ,  H02M3/07 ,  G11C13/00

CPC classification number: H02M3/07 ,  G11C5/145

Abstract: A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.

Abstract translation: 半导体存储器件通过包括用于根据电源电压的预定电平产生检测信号的电源电压电平检测器和用于产生频率为...的频率控制的振荡脉冲的振荡器，稳定地在宽范围的电源电压下工作 根据检测信号可变。 因此，升压电路的升压比，刷新电路的刷新周期和基板电压发生器的基板电压可以根据电源电压的变化自适应地变化。

公开(公告)号：US5130580A

公开(公告)日：1992-07-14

申请号：US550997

申请日：1990-07-11

Applicant: Dong-sun Min ,  Hong-sun Hwang ,  Soo-in Cho ,  Dae-Je Chin

Inventor： Dong-sun Min ,  Hong-sun Hwang ,  Soo-in Cho ,  Dae-Je Chin

IPC: G11C11/419 ,  G11C7/06 ,  G11C11/407 ,  G11C11/409

CPC classification number: G11C7/065

Abstract: A sense amplifier driving circuit for controlling sense amplifiers of high density semiconductor memory device by turning-on/off a driving transistor connected between an external voltage Vcc terminal and a ground voltage Vss terminal, comprises a bias circuit including a MOS transistor being connected to the driving MOS transistor to form a current mirror circuit therewith which is controlled by a sense amplifier enable clock and a constant current source having a MOS transistor with a bias voltage of an intermediate level between Vcc and Vss being applied to its gate terminal. The bias circuit is connected to the gate terminal of the driving transistor to control the gate voltage of the driving transistor, thereby reducing the peak current of a sense amplifier driving signal. Further, the driving signals are generated in the waveform having a linear dual slope, resulting in a decrease in power-noise. The bias circuit is connected to a clamping circuit having a comparator circuit to clamp the active restore voltage of the sense amplifier driving circuit, so that the active restore voltage can be maintained at the level of an internal voltage (approximately 4V), thereby preventing the distortion of the characteristics of the cell device and eliminating the necessity of additional standby current by enabling the sense amplifier only for the active restore operation. Further, the sense amplifier driving circuit comprises a constant circuit including two or more current mirror circuits which are sequentially activated, whereby the sense amplifier driving signals are made to have stable linear dual slopes.

Abstract translation: 一种读出放大器驱动电路，用于通过接通/断开连接在外部电压Vcc端子和接地电压Vss端子之间的驱动晶体管来控制高密度半导体存储器件的读出放大器，包括：偏置电路，包括MOS晶体管，连接到 驱动MOS晶体管与其形成电流镜像电路，其由读出放大器使能时钟控制，并且具有MOS晶体管的恒定电流源，其中Vcc和Vss之间的中间电平的偏置电压被施加到其栅极端子。 偏置电路连接到驱动晶体管的栅极端子，以控制驱动晶体管的栅极电压，从而降低读出放大器驱动信号的峰值电流。 此外，在具有线性双斜率的波形中产生驱动信号，导致功率噪声的降低。 偏置电路连接到具有比较器电路的钳位电路，以钳位读出放大器驱动电路的有效恢复电压，使得有效恢复电压可以保持在内部电压（大约4V）的水平，从而防止 通过使感测放大器仅用于主动恢复操作，从而消除了电池装置特性的失真，并消除了额外待机电流的必要性。 此外，读出放大器驱动电路包括一个恒定电路，该恒定电路包括被依次激活的两个或多个电流镜电路，从而使读出放大器驱动信号具有稳定的线性双斜率。

公开(公告)号：US09325006B2

公开(公告)日：2016-04-26

申请号：US13449109

申请日：2012-04-17

Applicant: Yun Ju Cho ,  Pil Sang Yun ,  Mi Sun Lee ,  Hae In Cho

Inventor： Yun Ju Cho ,  Pil Sang Yun ,  Mi Sun Lee ,  Hae In Cho

IPC: H01M4/485 ,  H01M2/14 ,  H01M4/505 ,  C01D1/20 ,  C01D1/22 ,  C01G1/02 ,  H01M4/525

CPC classification number: H01M4/505 ,  C01D1/20 ,  C01D1/22 ,  C01G1/02 ,  H01M4/525 ,  Y02E60/122

Abstract: A method for preparing a positive active material for a lithium ion secondary battery, the method including obtaining a mixture by mixing a lithium containing compound and metal oxide, distributing powder of a lithium containing compound into a furnace, and heat treating the mixture in the furnace, wherein a thermal decomposition temperature of the lithium containing compound power distributed into the furnace is lower than that of the lithium containing compound mixed with the metal oxide.

Abstract translation: 一种锂离子二次电池用正极活性物质的制造方法，其特征在于，通过混合含锂化合物和金属氧化物而得到混合物，将含锂化合物的粉末分配到炉中，并对所述炉内的混合物进行热处理 其中分配到炉中的含锂化合物功率的热分解温度低于与金属氧化物混合的含锂化合物的热分解温度。

公开(公告)号：US08715858B2

公开(公告)日：2014-05-06

申请号：US13445896

申请日：2012-04-12

Applicant: Sung Nim Jo ,  Mi Sun Lee ,  Hae In Cho

Inventor： Sung Nim Jo ,  Mi Sun Lee ,  Hae In Cho

IPC: H01M4/36 ,  H01M4/02 ,  H01M4/04

CPC classification number: H01M4/131 ,  C01G45/1242 ,  C01P2002/32 ,  C01P2004/03 ,  C01P2004/61 ,  H01M4/1391 ,  H01M4/505 ,  H01M2004/021 ,  Y10T29/49108

Abstract: A method for preparing a lithium manganese oxide positive active material for a lithium ion secondary battery, which has spherical spinel-type lithium manganese oxide particles having two or more different types of sizes, the method including uniformly mixing manganese oxide having two or more different types of sizes with a lithium containing compound, and heat treating the resultant mixture to obtain lithium manganese oxide.

Abstract translation: 一种制备锂离子二次电池用锂锰氧化物正极活性物质的方法，其具有两种以上不同尺寸的球形尖晶石型锂锰氧化物粒子，该方法包括均匀混合具有两种以上不同类型的氧化锰 与含锂化合物的尺寸，并对所得混合物进行热处理以获得锂锰氧化物。

公开(公告)号：US08503955B2

公开(公告)日：2013-08-06

申请号：US12839733

申请日：2010-07-20

Applicant: Kyu-Min Kang ,  Sang-In Cho ,  Heon-Jin Hong

Inventor： Kyu-Min Kang ,  Sang-In Cho ,  Heon-Jin Hong

IPC: H04B1/16

CPC classification number: H04B1/1027

Abstract: An apparatus for detecting a signal in a common frequency band includes: a signal processor configured to extract a selected band signal from received wireless signals by filtering the received wireless signal based on a frequency selection control signal, convert the extracted signal to a baseband signal, and detect a predetermined signal; a sensing signal determiner configured to determine existence of the signal, output a determination result, and outputs a frequency selection generating signal when the predetermined signal is absent; and a frequency selection controller configured to output the frequency selection control signal by selecting a target band among a plurality of previously decided bands.

Abstract translation: 用于检测公共频带中的信号的装置包括：信号处理器，被配置为基于频率选择控制信号对所接收的无线信号进行滤波，从接收到的无线信号中提取所选频带信号，将提取的信号转换为基带信号， 并检测预定信号; 感测信号确定器，被配置为确定信号的存在，输出确定结果，并且当所述预定信号不存在时，输出频率选择产生信号; 以及频率选择控制器，被配置为通过在多个先前确定的频带中选择目标频带来输出频率选择控制信号。