公开(公告)号：US07045850B2

公开(公告)日：2006-05-16

申请号：US10844783

申请日：2004-05-13

Applicant: Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

Inventor： Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

IPC: H01L29/76

CPC classification number: H01L27/11568 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

Abstract: The present invention discloses a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same. The method includes providing a semiconductor substrate having a nonvolatile memory region, a first region, and a second region. A triple layer composed of a tunnel oxide layer, a charge storing layer and a first deposited oxide layer on the semiconductor substrate is formed sequentially The triple layer on the semiconductor substrate except the nonvolatile memory region is then removed. A second deposited oxide layer is formed on an entire surface of the semiconductor substrate including the first and second regions from which the triple layer is removed. The second deposited oxide layer on the second region is removed, and a first thermal oxide layer is formed on the entire surface of the semiconductor substrate including the second region from which the second deposited oxide layer is removed. The semiconductor device can be manufactured according to the present invention to have a reduced processing time and a reduced change of impurity doping profile. The thickness of a blocking oxide layer and a high voltage gate oxide layer can be controlled.

Abstract translation: 本发明公开了一种具有浮动阱式非易失性存储单元的半导体器件及其制造方法。 该方法包括提供具有非易失性存储区域，第一区域和第二区域的半导体衬底。 依次形成由半导体衬底上的隧道氧化物层，电荷存储层和第一沉积氧化物层构成的三层，然后除去非易失性存储区域之外的半导体衬底上的三层。 第二沉积氧化物层形成在半导体衬底的包括去除三层的第一和第二区域的整个表面上。 去除第二区域上的第二沉积氧化物层，并且在包括除去第二沉积氧化物层的第二区域的半导体衬底的整个表面上形成第一热氧化物层。 可以根据本发明制造半导体器件以减少处理时间和降低杂质掺杂分布的变化。 可以控制阻挡氧化物层和高电压栅极氧化物层的厚度。

公开(公告)号：US20050186734A1

公开(公告)日：2005-08-25

申请号：US10786239

申请日：2004-02-24

Applicant: In-Wook Cho ,  Nae-In Lee ,  Kwang-Wook Koh ,  Geun-Jong Bae ,  Sang-Su Kim ,  Jin-Hee Kim ,  Sung-Ho Kim ,  Ki-Chul Kim

Inventor： In-Wook Cho ,  Nae-In Lee ,  Kwang-Wook Koh ,  Geun-Jong Bae ,  Sang-Su Kim ,  Jin-Hee Kim ,  Sung-Ho Kim ,  Ki-Chul Kim

IPC: H01L27/10 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/115 ,  H01L27/11568 ,  Y10S438/954

Abstract: A method of manufacturing a non-volatile semiconductor memory device begins by forming a dielectric layer pattern having an ONO composition on a substrate. A polysilicon layer is formed on the substrate including over the dielectric layer pattern. The polysilicon layer is patterned to form a split polysilicon layer pattern that exposes part of the dielectric layer pattern. The exposed dielectric layer is etched, and then impurities are implanted into portions of the substrate using the split polysilicon layer pattern as a mask to thereby form a source region having a vertical profile in the substrate.

Abstract translation: 制造非易失性半导体存储器件的方法是通过在衬底上形成具有ONO组成的电介质层图案而开始的。 在包括在电介质层图案上的衬底上形成多晶硅层。 图案化多晶硅层以形成暴露部分介电层图案的分裂多晶硅层图案。 暴露的电介质层被蚀刻，然后使用分离多晶硅层图案作为掩模将杂质注入到衬底的部分中，从而在衬底中形成具有垂直轮廓的源区。

公开(公告)号：US20050048702A1

公开(公告)日：2005-03-03

申请号：US10953553

申请日：2004-09-30

Applicant: Geum-Jong Bae ,  Nae-In Lee ,  Sang Kim ,  Ki Kim ,  Jin-Hee Kim ,  In-Wook Cho ,  Sung-Ho Kim ,  Kwang-Wook Koh

Inventor： Geum-Jong Bae ,  Nae-In Lee ,  Sang Kim ,  Ki Kim ,  Jin-Hee Kim ,  In-Wook Cho ,  Sung-Ho Kim ,  Kwang-Wook Koh

IPC: H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L21/335

CPC classification number: H01L29/792 ,  H01L29/7923 ,  Y10S438/954

Abstract: A local SONOS structure having a two-piece gate and a self-aligned ONO structure includes: a substrate; an ONO structure on the substrate; a first gate layer on and aligned with the ONO structure; a gate insulator on the substrate aside the ONO structure; and a second gate layer on the first gate layer and on the gate insulator. The first and second gate layers are electrically connected together. Together, the ONO structure and first and second gate layers define at least a 1-bit local SONOS structure. A corresponding method of manufacture includes: providing a substrate; forming an ONO structure on the substrate; forming a first gate layer on and aligned with the ONO structure; forming a gate insulator on the substrate aside the ONO structure; forming a second gate layer on the first gate layer and on the gate insulator; and electrically connecting the first and second gate layers.

Abstract translation: 具有两件式门和自对准ONO结构的本地SONOS结构包括：衬底; 基底上的ONO结构; 在ONO结构上并与ONO结构对准的第一栅极层; 衬底上的栅极绝缘体旁边的ONO结构; 以及在第一栅极层上和栅极绝缘体上的第二栅极层。 第一和第二栅极层电连接在一起。 ONO结构和第一和第二栅极层一起定义至少1位本地SONOS结构。 相应的制造方法包括：提供衬底; 在基板上形成ONO结构; 在ONO结构上形成第一栅极层并与其结合; 在衬底上形成栅极绝缘体，除了ONO结构; 在第一栅极层和栅极绝缘体上形成第二栅极层; 并且电连接第一和第二栅极层。

公开(公告)号：US07700437B2

公开(公告)日：2010-04-20

申请号：US12183553

申请日：2008-07-31

Applicant: Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim

Inventor： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim

IPC: H01L21/8247

CPC classification number: H01L29/42352 ,  H01L21/28282 ,  H01L29/7923 ,  Y10S438/954

Abstract: In a non-volatile memory device with a buried control gate, the effective channel length of the control gate is increased to restrain punchthrough, and a region for storing charge is increased for attaining favorably large capacity. A method of fabricating the memory device includes forming the control gate within a trench formed in a semiconductor substrate, and forming charge storing regions in the semiconductor substrate on both sides of the control gate in a self-aligning manner, thereby allowing for multi-level cell operation.

Abstract translation: 在具有埋地控制栅极的非易失性存储器件中，增加控制栅极的有效沟道长度以限制穿通，并且增加用于存储电荷的区域以获得有利的大容量。 一种制造存储器件的方法包括：在形成于半导体衬底中的沟槽内形成控制栅极，并以自对准的方式在控制栅极两侧的半导体衬底中形成电荷存储区域，从而允许多级 电池操作。

公开(公告)号：US07371640B2

公开(公告)日：2008-05-13

申请号：US11378505

申请日：2006-03-17

Applicant: Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

Inventor： Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

IPC: H01L21/336

CPC classification number: H01L27/11568 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

Abstract: The present invention discloses a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same. The method includes providing a semiconductor substrate having a nonvolatile memory region, a first region, and a second region. A triple layer composed of a tunnel oxide layer, a charge storing layer and a first deposited oxide layer on the semiconductor substrate is formed sequentially. The triple layer on the semiconductor substrate except the nonvolatile memory region is then removed. A second deposited oxide layer is formed on an entire surface of the semiconductor substrate including the first and second regions from which the triple layer is removed. The second deposited oxide layer on the second region is removed, and a first thermal oxide layer is formed on the entire surface of the semiconductor substrate including the second region from which the second deposited oxide layer is removed. The semiconductor device can be manufactured according to the present invention to have a reduced processing time and a reduced change of impurity doping profile. The thickness of a blocking oxide layer and a high voltage gate oxide layer can be controlled.

Abstract translation: 本发明公开了一种具有浮动阱式非易失性存储单元的半导体器件及其制造方法。 该方法包括提供具有非易失性存储区域，第一区域和第二区域的半导体衬底。 顺序地形成由半导体衬底上的隧道氧化物层，电荷存储层和第一沉积氧化物层组成的三层。 然后除去非易失性存储区域之外的半导体衬底上的三层。 第二沉积氧化物层形成在半导体衬底的包括去除三层的第一和第二区域的整个表面上。 去除第二区域上的第二沉积氧化物层，并且在包括除去第二沉积氧化物层的第二区域的半导体衬底的整个表面上形成第一热氧化物层。 可以根据本发明制造半导体器件以减少处理时间和降低杂质掺杂分布的变化。 可以控制阻挡氧化物层和高电压栅极氧化物层的厚度。

公开(公告)号：US07179709B2

公开(公告)日：2007-02-20

申请号：US11146501

申请日：2005-06-07

Applicant: Sang-Su Kim ,  Geum-Jong Bae ,  In-Wook Cho ,  Jin-Hee Kim

Inventor： Sang-Su Kim ,  Geum-Jong Bae ,  In-Wook Cho ,  Jin-Hee Kim

IPC: H01L21/336 ,  H01L21/4763 ,  H01L21/3205

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/11573 ,  Y10S438/954

Abstract: in methods of fabricating a non-volatile memory device having a local silicon-oxide-nitride-oxide-silicon (SONOS) gate structure, a semiconductor substrate having a cell transistor area, a high voltage transistor area, and a low voltage transistor area, is prepared. At least one memory storage pattern defining a cell gate insulating area on the semiconductor substrate within the cell transistor area is formed. An oxidation barrier layer is formed on the semiconductor substrate within the cell gate insulating area. A lower gate insulating layer is formed on the semiconductor substrate within the high voltage transistor area. A conformal upper insulating layer is formed on the memory storage pattern, the oxidation barrier layer, and the lower gate insulating layer. A low voltage gate insulating layer having a thickness which is less than a combined thickness of the upper insulating layer and the lower gate insulating layer is formed on the semiconductor substrate within the low voltage transistor area.

Abstract translation: 在制造具有局部氧化硅 - 氮化物 - 氧化物 - 硅（SONOS）栅极结构的非易失性存储器件的方法中，具有单元晶体管区域，高压晶体管区域和低压晶体管区域的半导体衬底， 准备好了 形成在单元晶体管区域内的半导体衬底上限定单元栅极绝缘区域的至少一个存储器存储图案。 在单元栅极绝缘区域内的半导体衬底上形成氧化阻挡层。 在高电压晶体管区域内的半导体衬底上形成下栅极绝缘层。 在存储器存储图案，氧化阻挡层和下栅极绝缘层上形成保形的上绝缘层。 在低压晶体管区域内的半导体衬底上形成厚度小于上绝缘层和下栅极绝缘层的组合厚度的低压栅极绝缘层。

公开(公告)号：US20050153514A1

公开(公告)日：2005-07-14

申请号：US11033156

申请日：2005-01-12

Applicant: Jai-Dong Lee ,  Ki-Chul Kim ,  In-Wook Cho

Inventor： Jai-Dong Lee ,  Ki-Chul Kim ,  In-Wook Cho

IPC: H01L27/115 ,  H01L21/314 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/3205 ,  H01L21/31

CPC classification number: H01L21/022 ,  H01L21/02329 ,  H01L21/0234 ,  H01L21/3144 ,  H01L27/11568 ,  H01L29/66833

Abstract: A method for manufacturing a dielectric layer structure for a non-volatile memory cell is provided. A method includes forming a first dielectric layer for tunneling on a semiconductor substrate, a second dielectric layer on the first dielectric layer to store charges, nitrogenizing surface of the second dielectric layer, and forming a third dielectric layer the nitridedsecond dielectric layer.

Abstract translation: 提供一种用于制造用于非易失性存储单元的电介质层结构的方法。 一种方法包括形成用于在半导体衬底上隧穿的第一电介质层，在第一电介质层上形成第二电介质层以存储电荷，使第二电介质层的氮化表面，以及形成第三介电层氮化二次介电层。

公开(公告)号：US06815764B2

公开(公告)日：2004-11-09

申请号：US10388631

申请日：2003-03-17

Applicant: Geum-Jong Bae ,  Nae-In Lee ,  Sang Su Kim ,  Ki Chul Kim ,  Jin-Hee Kim ,  In-Wook Cho ,  Sung-Ho Kim ,  Kwang-Wook Koh

Inventor： Geum-Jong Bae ,  Nae-In Lee ,  Sang Su Kim ,  Ki Chul Kim ,  Jin-Hee Kim ,  In-Wook Cho ,  Sung-Ho Kim ,  Kwang-Wook Koh

IPC: H01L29792

CPC classification number: H01L29/792 ,  H01L29/7923 ,  Y10S438/954

Abstract: A local SONOS structure having a two-piece gate and a self-aligned ONO structure includes: a substrate; an ONO structure on the substrate; a first gate layer on and aligned with the ONO structure; a gate insulator on the substrate aside the ONO structure; and a second gate layer on the first gate layer and on the gate insulator. The first and second gate layers are electrically connected together. Together, the ONO structure and first and second gate layers define at least a 1-bit local SONOS structure. A corresponding method of manufacture includes: providing a substrate; forming an ONO structure on the substrate; forming a first gate layer on and aligned with the ONO structure; forming a gate insulator on the substrate aside the ONO structure; forming a second gate layer on the first gate layer and on the gate insulator; and electrically connecting the first and second gate layers.

Abstract translation: 具有两件式门和自对准ONO结构的本地SONOS结构包括：衬底; 基底上的ONO结构; 在ONO结构上并与ONO结构对准的第一栅极层; 衬底上的栅极绝缘体旁边的ONO结构; 以及在第一栅极层上和栅极绝缘体上的第二栅极层。 第一和第二栅极层电连接在一起。 ONO结构和第一和第二栅极层一起定义至少1位本地SONOS结构。 相应的制造方法包括：提供衬底; 在基板上形成ONO结构; 在ONO结构上形成第一栅极层并与其结合; 在衬底上形成栅极绝缘体，除了ONO结构; 在第一栅极层和栅极绝缘体上形成第二栅极层; 并且电连接第一和第二栅极层。

公开(公告)号：US07718504B2

公开(公告)日：2010-05-18

申请号：US11535934

申请日：2006-09-27

Applicant: Sang-Su Kim ,  In-Wook Cho ,  Myeong-Cheol Kim ,  Sung-Woo Lee ,  Jin-Hee Kim ,  Doo-Youl Lee ,  Sung-Ho Kim

Inventor： Sang-Su Kim ,  In-Wook Cho ,  Myeong-Cheol Kim ,  Sung-Woo Lee ,  Jin-Hee Kim ,  Doo-Youl Lee ,  Sung-Ho Kim

IPC: H01L21/76 ,  H01L21/46

CPC classification number: H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: Disclosed is a semiconductor device having an align key and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a cell area and an align key area. An isolation layer that defines a cell active area is disposed in the cell area of the semiconductor substrate. A cell charge storage layer pattern is disposed across the cell active area. An align charge storage layer pattern is disposed in the align key area of the semiconductor substrate. An align trench self-aligned with the align charge storage layer pattern is formed in the align key area of the semiconductor substrate.

Abstract translation: 公开了具有对准键的半导体器件及其制造方法。 半导体器件包括具有单元区域和对准键区域的半导体衬底。 限定电池有源区的隔离层设置在半导体衬底的单元区域中。 电池电荷存储层图案跨越电池有源区域设置。 对准电荷存储层图案设置在半导体衬底的对准键区域中。 在对准电荷存储层图案中自对准的对准沟槽形成在半导体衬底的对准键区域中。

公开(公告)号：US07566928B2

公开(公告)日：2009-07-28

申请号：US11269624

申请日：2005-11-09

Applicant: Sung-ho Kim ,  Nae-in Lee ,  Kwang-wook Koh ,  Geum-jong Bae ,  Ki-chul Kim ,  Jin-hee Kim ,  In-wook Cho ,  Sang-su Kim

Inventor： Sung-ho Kim ,  Nae-in Lee ,  Kwang-wook Koh ,  Geum-jong Bae ,  Ki-chul Kim ,  Jin-hee Kim ,  In-wook Cho ,  Sang-su Kim

IPC: H01L29/788

CPC classification number: H01L27/11568 ,  G11C16/0416 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: Byte-operational nonvolatile semiconductor memory devices are capable of erasing stored data one byte at a time. A byte memory cell may include a memory cell array of 1-byte memory transistors. The 1-byte memory transistors may be arranged in one direction, each including a junction region and a channel region formed in an active region. A byte memory cell may include a byte select transistor. The select transistor may be disposed in the active region and including a junction region that is directly adjacent to a junction of each of the 1-byte memory transistors. The byte select transistor may be disposed over or under the 1-byte memory transistors perpendicular to the arranged direction of the 1-byte memory transistors.

Abstract translation: 字节操作的非易失性半导体存储器件能够一次一个字节地擦除存储的数据。 字节存储单元可以包括1字节存储晶体管的存储单元阵列。 1字节存储晶体管可以沿一个方向布置，每个包括结区域和形成在有源区域中的沟道区域。 字节存储单元可以包括字节选择晶体管。 选择晶体管可以设置在有源区域中并且包括与每个1字节存储晶体管的结直接相邻的结区域。 字节选择晶体管可以布置在垂直于1字节存储晶体管的排列方向的1字节存储晶体管的上方或下方。