Matrix logic circuit network suitable for large-scale integration
    11.
    发明授权
    Matrix logic circuit network suitable for large-scale integration 失效
    矩阵逻辑电路网适合大规模集成

    公开(公告)号:US4910508A

    公开(公告)日:1990-03-20

    申请号:US808377

    申请日:1985-12-16

    申请人: Isamu Yamazaki

    发明人: Isamu Yamazaki

    IPC分类号: G06F7/50 G06F7/505 H03K19/177

    摘要: A matrix logic circuit network comprises a great number of interconnected logic gates. Input and output lines of the logic gates are arranged in the matrix array. By rearranging the input and output lines of the matrix in accordance with a sort algorithm, direct connection points of the input and output lines to which the same signals are allotted and connecting elements forming logic gates located at given intersections of the input and output lines are arranged within a diagonal area with a limited width, which extends along a diagonal line of the matrix.

    摘要翻译: 矩阵逻辑电路网络包括大量互连的逻辑门。 逻辑门的输入和输出线被布置在矩阵阵列中。 通过根据分类算法重新排列矩阵的输入和输出线,分配相同信号的输入和输出线的直接连接点和形成位于输入和输出线的给定交点处的逻辑门的连接元件是 布置在具有有限宽度的对角区域内,该对角线区域沿矩阵的对角线延伸。

    Index limited continuous operation vector processor
    12.
    发明授权
    Index limited continuous operation vector processor 失效
    指数有限连续运算矢量处理器

    公开(公告)号:US4823258A

    公开(公告)日:1989-04-18

    申请号:US98313

    申请日:1987-09-18

    申请人: Isamu Yamazaki

    发明人: Isamu Yamazaki

    IPC分类号: G06F17/16 G06F15/78 G06F1/00

    CPC分类号: G06F15/8061

    摘要: The vector processor of the present invention is designed to have a first function for classifying, generating and storing in advance a separate index set by judging the attribute of specified data and a second function for continuously performing operand access only for the index value belonging to the specified index set out of the index sets generated by the first function, thus avoiding the deterioration of the efficiency of pipeline processing even when the calculation of array data has different operation content according to the attributes of the specified data. Accordingly it can perform continuous calculation of a plurality of different conditioned expressions at high speed by arranging it to operate the first and the second functions concurrently with the value resulting from the operation by the second function being used by the first function as a data for discriminating the attribute of the data.

    摘要翻译: 本发明的向量处理器被设计成具有第一功能,用于通过判断指定数据的属性来预先分类,生成和存储单独的索引集合,以及用于仅对属于该属性的索引值连续执行操作数访问的第二功能 由第一功能生成的索引集中指定的索引,即使当根据指定数据的属性计算阵列数据具有不同的操作内容时,也避免了流水线处理的效率的劣化。 因此,通过将第一功能所使用的第二功能的操作所产生的值与第一功能和第二功能同时运行,可以高速执行多个不同的条件表达式的连续计算,作为用于区别的数据 数据的属性。

    Microprogram controlled system
    13.
    发明授权
    Microprogram controlled system 失效
    微程序控制系统

    公开(公告)号:US4130869A

    公开(公告)日:1978-12-19

    申请号:US779561

    申请日:1977-03-21

    IPC分类号: G06F9/22 G06F9/30 G06F9/16

    CPC分类号: G06F9/223

    摘要: A microprogram controlled system to which is applied the vertical type microprogramming technique. Microinstructions fetched from a control stage are decoded in a control decoder, which controls gates of registers in a central processor to execute the microinstructions. The microinstructions include an extension field in the format to modify the functions thereof.

    摘要翻译: 微程序控制系统采用垂直式微程序技术。 从控制级提取的微指令在控制解码器中解码,控制解码器控制中央处理器中的寄存器的门执行微指令。 微指令包括以修改其功能的格式的扩展字段。

    Cartridge paint-charging method and device therefor
    15.
    发明授权
    Cartridge paint-charging method and device therefor 有权
    墨盒涂装方法及装置

    公开(公告)号:US06612345B1

    公开(公告)日:2003-09-02

    申请号:US09720244

    申请日:2001-01-04

    IPC分类号: B05B1214

    摘要: An apparatus for replenishing paint into a paint cartridge (25), which is capable of putting paint in respiratory circulation while the cartridge is in a waiting state. The apparatus includes a replenishing valve (61) which is capable of feeding paint to and from a paint chamber (30) of the paint cartridge (25) which is set on a replenishing stool (52), and a respiratory paint circulation valve (91) which is capable of feeding paint-extruding thinner to and from a thinner chamber (31) of the cartridge. After switching the replenishing valve (61) to a drain or discharge side, paint-extruding thinner is supplied from the respiratory paint circulation valve (91) to push paint out of the paint chamber (30) of the cartridge (25). Then, after switching the replenishing valve (61) to the side of a paint supply source, paint-extruding thinner is discharged by way of the respiratory paint circulation valve (91) to suck paint into the paint chamber (30). As a consequence, paint in the cartridge (25) is put in respiratory circulation to prevent separation and sedimentation of pigment components of the paint.

    摘要翻译: 一种用于将油漆补充到油漆盒(25)中的装置,当油墨盒处于等待状态时,能够将油漆置于呼吸循环中。 该装置包括补充阀(61),该补充阀能够向设置在补充粪便(52)上的油漆盒(25)的油漆室(30)和从呼吸涂料循环阀(91) ),其能够向盒的较薄室(31)供给涂料 - 挤出稀释剂。 在将补充阀(61)切换到泄放或排出侧后,从呼吸涂料循环阀(91)供给涂料挤出稀释剂,以将油漆推出墨盒(25)的涂料室(30)。 然后,在将补充阀(61)切换到涂料供给源侧后,通过呼吸用涂料循环阀(91)排出涂料挤出稀释剂,将涂料吸入涂料室(30)。 因此,将药筒(25)中的油漆置于呼吸循环中,以防止油漆颜料成分分离和沉淀。

    Disposable absorbent article
    16.
    发明授权
    Disposable absorbent article 失效
    一次性吸收制品

    公开(公告)号:US5662637A

    公开(公告)日:1997-09-02

    申请号:US351190

    申请日:1994-11-30

    IPC分类号: A61F13/494 A61F5/44 A61F13/15

    摘要: A disposable absorbent article such as a disposable diaper including first stretchable side flaps extending over transversely opposite outer zones of the diaper and second stretchable side flaps functioning as liquid-barriers each having a proximal edge and a distal edge arranged so as to define an exposed zone of a topsheet along each of transversely opposite side edge surfaces of a liquid-absorbent core and thereby, if a quantity of liquid excretions gets over the distal edge of the second side flaps, it can be absorbed by the liquid-absorbent core through the exposed zones.

    摘要翻译: 一次性吸收制品,例如一次性尿布,其包括在尿布的横向相对的外部区域上延伸的第一可拉伸侧翼片和用作液体屏障的第二可拉伸侧翼片,每个侧壁具有近侧边缘和远侧边缘,其布置成限定暴露区域 的吸液芯的横向相对的侧边缘表面的顶片,从而如果一定量的液体排泄物越过第二侧翼的远端边缘,则可通过暴露的吸收芯吸收吸液芯 区域。

    Information-processing system having a single chip arithmetic control
unit with means for prefetching instructions
    17.
    发明授权
    Information-processing system having a single chip arithmetic control unit with means for prefetching instructions 失效
    信息处理系统具有单芯片运算控制单元,具有用于预取指令的装置

    公开(公告)号:US4734849A

    公开(公告)日:1988-03-29

    申请号:US886807

    申请日:1986-07-16

    IPC分类号: G06F9/38 G06F9/00

    摘要: In a one-chip high density arithmetic control unit capable of prefetching user's instructions from main memory, an arithmetic logic unit (ALU) subtracts the contents of a location counter holding the address of the next instruction to be executed, from the contents of a memory address register holding an address into which data will be written. The difference is fed through the gates connected to the ALU for determining whether or not prefetched instructions will have to be refetched. An address matching mechanism provided outside the one-chip arithmetic control unit includes a comparator for comparing memory addresses to a preset execution stop address. The output signal of the comparator is stored in a memory section which is provided to correspond to the prefetched instruction buffer, and when an instruction stored in the prefetched instruction buffer is transferred to an instruction register, the signal stored in the corresponding memory section is also read out and used to determine whether to stop execution. Further, whenever access is made to main memory a signal indicating whether the access is legal is externally generated and may be stored in a second memory section. Like the address matching signal, this signal is read out when the corresponding instruction from the prefeteched instruction buffer is transferred to the instruction register. An illegal address interruption is produced when this signal indicates that the address was illegal.

    Manufacturing apparatus
    18.
    发明授权
    Manufacturing apparatus 失效
    制造设备

    公开(公告)号:US4674670A

    公开(公告)日:1987-06-23

    申请号:US762823

    申请日:1985-08-06

    IPC分类号: B23K20/00 H01L21/00 B23K1/00

    摘要: The invention relates to a manufacturing apparatus which comprises moving means which continuously moves the works that are transferred along a frame chute, and detector means which detects at least a portion of the work that is moved. The moving means is controlled by kind-of-work data and by a work position signal from the detector means, and the work is set to a predetermined position. Hence, even a work of a different kind can be set to an optimum bonding position without the need of exchanging the unit, making it possible to perform the operation fully automatically and to meet general purposes.Further, provision is made of means which moves the frame chute in a direction at right angles with the direction in which the work is moved, so that even that work that has different widths and shapes in the widthwise direction can be placed in position and subjected to the bonding fully automatically.The detector means can be provided not only at the bonding position but also at a position on the upstream side having a relation relative to the bonding position.The invention can be adapted particularly effectively to a wire bonder and a pellet bonder.

    摘要翻译: 本发明涉及一种制造装置,其包括连续地移动沿着框架槽传送的工件的移动装置和检测至少一部分被移动的工件的检测器装置。 移动装置由工作数据和来自检测装置的工作位置信号控制,工件被设定到预定位置。 因此,即使不同种类的工作也可以被设定为最佳的结合位置,而不需要更换单元,使得可以完全自动地执行操作并且达到一般目的。 此外,提供了使框架滑槽沿与工件移动方向成直角的方向移动的装置,使得即使在宽度方向上具有不同宽度和形状的工件也可以被放置就位 完全自动粘接。 检测器装置不仅可以在接合位置处设置,而且还可以设置在上游侧的位置,具有相对于接合位置的关系。 本发明可以特别有效地适用于焊线机和颗粒接合机。

    Shift circuit having a plurality of cascade-connected data selectors
    19.
    发明授权
    Shift circuit having a plurality of cascade-connected data selectors 失效
    移位电路具有多个级联连接的数据选择器

    公开(公告)号:US4472788A

    公开(公告)日:1984-09-18

    申请号:US296859

    申请日:1981-08-27

    申请人: Isamu Yamazaki

    发明人: Isamu Yamazaki

    CPC分类号: G11C19/00 G06F5/01 G06F5/015

    摘要: A shift circuit comprises a plurality of stages of data selectors, a first data selector, a second data selector and a temporary register. The data selectors shift an n-bit input data by m bits which are specified by a shifting amount data and produces a first output data or a second output data. The first and second data selectors selectively output the first and second output data in accordance with shift direction. The temporary register comprises n bits for storing a data which is not selected by said first or second data selector.

    摘要翻译: 移位电路包括多级数据选择器,第一数据选择器,第二数据选择器和临时寄存器。 数据选择器将由移位量数据指定的n位输入数据移位m位,并产生第一输出数据或第二输出数据。 第一和第二数据选择器根据移位方向选择性地输出第一和第二输出数据。 临时寄存器包括用于存储未被所述第一或第二数据选择器选择的数据的n位。

    Information processing system including a one-chip arithmetic control
unit
    20.
    发明授权
    Information processing system including a one-chip arithmetic control unit 失效
    信息处理系统,包括单片机运算控制单元

    公开(公告)号:US4466055A

    公开(公告)日:1984-08-14

    申请号:US244623

    申请日:1981-03-17

    摘要: In an information processing system in which an arithmetic control unit is formed on one chip by very large scale integration and is connected to external devices by a common bus, microinstructions from an externally-connected control memory, memory information output from an external main memory and information output from I/O devices, can be received by the arithmetic control unit on the common bus. An external setting signal for selecting whether the instruction system of the arithmetic control unit is to be enabled or disabled is input to the arithmetic control unit on the common bus simultaneously with the fetching of a microinstruction. A bus width setting signal from an I/O device is also input to the arithmetic control unit on the common bus simultaneously with the fetching of a microinstruction, and the CPU determines whether the data width of an I/O device is 8 bits or 16 bits. An interruption signal from an I/O device and a signal indicating an abnormal condition of a power source, for example, may be input to the arithmetic control unit from external devices on the common bus as part of a group of external signals occupying only a portion of the common bus simultaneously with the fetching of a microinstruction on the remaining portion of the common bus. When exchanging a plurality of kinds of data with different phases between the arithmetic control unit and external devices on the common bus, an external status signal unique to each phase is input to the arithmetic control unit on a common signal line in synchronism with each phase.

    摘要翻译: 在一种信息处理系统中,其中通过非常大规模的集成在一个芯片上形成运算控制单元,并且通过公共总线连接到外部设备,来自外部连接的控制存储器的微指令,从外部主存储器输出的存储器信息和 I / O设备输出的信息可由公共总线上的运算控制单元接收。 用于选择运算控制单元的指令系统是否被使能或禁用的外部设置信号在获取微指令时同时在公共总线上输入到运算控制单元。 来自I / O设备的总线宽度设置信号也被同时输入到公共总线上的算术控制单元,同时获取微指令,并且CPU确定I / O设备的数据宽度是8位还是16 位。 来自I / O设备的中断信号和指示电源异常状态的信号例如可以从公共总线上的外部设备输入到算术控制单元,作为仅占用一个 公共总线的一部分同时在公共总线的剩余部分上取出微指令。 当在公共总线上的算术控制单元和外部设备之间交换具有不同相位的多种数据时,每个相位独有的外部状态信号与每个相位同步地在公共信号线上输入到运算控制单元。