公开(公告)号：US07965578B2

公开(公告)日：2011-06-21

申请号：US12954492

申请日：2010-11-24

Applicant: Jayesh R. Bhakta ,  Jeffrey C. Solomon

Inventor： Jayesh R. Bhakta ,  Jeffrey C. Solomon

IPC: G11C8/00

Abstract: A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated by a first number of chip-select signals. The circuit is configurable to receive bank address signals, a second number of chip-select signals, and row/column address signals from the computer system. The circuit is further configurable to generate phase-locked clock signals in response to clock signals received from the computer system and to provide the first number of chip-select signals to the first number of ranks in response to the phase-locked clock signals, the received bank address signals, the received second number of chip-select signals, and at least one of the received row/column address signals.

公开(公告)号：US20110110047A1

公开(公告)日：2011-05-12

申请号：US12939915

申请日：2010-11-04

Applicant: Robert S. Pauley ,  Jayesh R. Bhakta ,  William M. Gervasi ,  Chi She Chen ,  Jose Delvalle

Inventor： Robert S. Pauley ,  Jayesh R. Bhakta ,  William M. Gervasi ,  Chi She Chen ,  Jose Delvalle

IPC: H05K7/20

CPC classification number: H05K1/0203 ,  H05K1/144 ,  H05K2201/10189 ,  H05K2201/1056 ,  H05K2201/2018 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/4913

Abstract: A module is electrically connectable to a computer system. The module includes a first surface and a first plurality of circuit packages coupled to the first surface. The module further includes a second surface and a second plurality of circuit packages coupled to the second surface. The second surface faces the first surface. The module further includes at least one thermal conduit positioned between the first surface and the second surface. The at least one thermal conduit is in thermal communication with the first plurality of circuit packages and the second plurality of circuit packages.

Abstract translation: 模块可电连接到计算机系统。 模块包括耦合到第一表面的第一表面和第一多个电路封装。 该模块还包括耦合到第二表面的第二表面和第二多个电路封装。 第二表面面向第一表面。 模块还包括位于第一表面和第二表面之间的至少一个热导管。 所述至少一个热导管与所述第一多个电路封装件和所述第二多个电路封装体热连通。

公开(公告)号：US07916574B1

公开(公告)日：2011-03-29

申请号：US12955711

申请日：2010-11-29

Applicant: Jeffrey C. Solomon ,  Jayesh R. Bhakta

Inventor： Jeffrey C. Solomon ,  Jayesh R. Bhakta

IPC: G11C8/00

CPC classification number: G06F13/1673 ,  G06F12/00 ,  G06F13/00 ,  G06F13/4243 ,  G06F13/4282 ,  G11C5/04 ,  G11C7/1072 ,  G11C15/00

Abstract: A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated by a first number of chip-select signals. The circuit is configurable to receive bank address signals, a second number of chip-select signals, and row/column address signals from the computer system. The circuit is further configurable to generate phase-locked clock signals in response to clock signals received from the computer system, to selectively isolate one or more loads of the first number of ranks from the computer system, and to translate between a system memory domain and a physical memory domain of the memory module.

Abstract translation: 电路被配置为安装在可连接到计算机系统的存储器模块上，以便电耦合到存储器模块上的多个存储器件。 存储器模块具有由第一数量的芯片选择信号激活的第二数量的双数据速率（DDR）存储器件。 电路可配置为接收来自计算机系统的存储体地址信号，第二数量的芯片选择信号和行/列地址信号。 该电路还可配置为响应于从计算机系统接收的时钟信号而产生锁相时钟信号，以便选择性地将计算机系统中的第一数量级别的一个或多个负载隔离，并在系统存储器域和 存储器模块的物理内存域。

公开(公告)号：US07864627B2

公开(公告)日：2011-01-04

申请号：US12577682

申请日：2009-10-12

Applicant: Jayesh R. Bhakta ,  Jeffrey C. Solomon

Inventor： Jayesh R. Bhakta ,  Jeffrey C. Solomon

IPC: G11C8/16

CPC classification number: G11C8/12 ,  G06F12/0207 ,  G06F12/0215 ,  G11C5/04 ,  G11C5/066 ,  G11C7/1048 ,  G11C2207/105 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2203/1572 ,  Y02P70/611

Abstract: A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The plurality of memory devices has a first number of memory devices. The circuit comprises a logic element configurable to receive a set of input signals from the computer system. The circuit further comprising a register and a phase-lock loop circuit, the phase-lock loop circuit configurable to be operatively coupled to the plurality of memory devices, the logic element, and the register. The set of input signals corresponds to a second number of memory devices smaller than the first number of memory devices.

Abstract translation: 电路被配置为安装在可连接到计算机系统的存储器模块上，以便电耦合到存储器模块上的多个存储器件。 多个存储器件具有第一数量的存储器件。 电路包括可配置为从计算机系统接收一组输入信号的逻辑元件。 所述电路还包括寄存器和锁相环电路，所述锁相环电路可配置为可操作地耦合到所述多个存储器件，所述逻辑元件和所述寄存器。 该组输入信号对应于小于第一数量的存储器件的第二数量的存储器件。

公开(公告)号：US20100110642A1

公开(公告)日：2010-05-06

申请号：US12606136

申请日：2009-10-26

Applicant: Robert S. Pauley ,  Jayesh R. Bhakta ,  William M. Gervasi ,  Chi She Chen ,  Jose Delvalle

Inventor： Robert S. Pauley ,  Jayesh R. Bhakta ,  William M. Gervasi ,  Chi She Chen ,  Jose Delvalle

IPC: H05K7/20 ,  F28F13/00 ,  H01L23/34

CPC classification number: H05K1/0203 ,  H05K1/144 ,  H05K2201/10189 ,  H05K2201/1056 ,  H05K2201/2018 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/4913

Abstract: A module is electrically connectable to a computer system. The module includes a plurality of electrical contacts which are electrically connectable to the computer system. The module further includes a first surface and a first plurality of circuits coupled to the first surface. The first plurality of circuits is in electrical communication with the electrical contacts. The module further includes a second surface and a second plurality of circuits coupled to the second surface. The second plurality of circuits is in electrical communication with the electrical contacts. The second surface faces the first surface. The module further includes at least one thermally conductive layer positioned between the first surface and the second surface. The at least one thermally conductive layer is in thermal communication with the first plurality of circuits, the second plurality of circuits, and a first set of the plurality of electrical contacts.

Abstract translation: 模块可电连接到计算机系统。 模块包括可电连接到计算机系统的多个电触点。 模块还包括耦合到第一表面的第一表面和第一多个电路。 第一组多个电路与电触点电连通。 模块还包括耦合到第二表面的第二表面和第二多个电路。 第二组电路与电触点电连通。 第二表面面向第一表面。 模块还包括位于第一表面和第二表面之间的至少一个导热层。 所述至少一个导热层与所述第一多个电路，所述第二多个电路和所述多个电触头的第一组热连通。

公开(公告)号：US20100091540A1

公开(公告)日：2010-04-15

申请号：US12577682

申请日：2009-10-12

Applicant: Jayesh R. Bhakta ,  Jeffrey C. Solomon

Inventor： Jayesh R. Bhakta ,  Jeffrey C. Solomon

IPC: G11C5/02 ,  G11C8/16 ,  G11C7/00

CPC classification number: G11C8/12 ,  G06F12/0207 ,  G06F12/0215 ,  G11C5/04 ,  G11C5/066 ,  G11C7/1048 ,  G11C2207/105 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2203/1572 ,  Y02P70/611

Abstract: A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The plurality of memory devices has a first number of memory devices. The circuit comprises a logic element configurable to receive a set of input signals from the computer system. The circuit further comprising a register and a phase-lock loop circuit, the phase-lock loop circuit configurable to be operatively coupled to the plurality of memory devices, the logic element, and the register. The set of input signals corresponds to a second number of memory devices smaller than the first number of memory devices.

Abstract translation: 电路被配置为安装在可连接到计算机系统的存储器模块上，以便电耦合到存储器模块上的多个存储器件。 多个存储器件具有第一数量的存储器件。 电路包括可配置为从计算机系统接收一组输入信号的逻辑元件。 所述电路还包括寄存器和锁相环电路，所述锁相环电路可配置为可操作地耦合到所述多个存储器件，所述逻辑元件和所述寄存器。 该组输入信号对应于小于第一数量的存储器件的第二数量的存储器件。

公开(公告)号：US07375970B2

公开(公告)日：2008-05-20

申请号：US11775125

申请日：2007-07-09

Applicant: Robert S. Pauley ,  Jayesh R. Bhakta ,  William M. Gervasi ,  Chi She Chen ,  Jose Delvalle

Inventor： Robert S. Pauley ,  Jayesh R. Bhakta ,  William M. Gervasi ,  Chi She Chen ,  Jose Delvalle

IPC: H05K7/20

CPC classification number: H05K1/0203 ,  H05K1/144 ,  H05K2201/10189 ,  H05K2201/1056 ,  H05K2201/2018 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/4913

Abstract: A module is electrically connectable to a computer system. The module includes at least one multilayer structure having a plurality of electrical contacts which are electrically connectable to the computer system. The module further includes a first printed circuit board coupled to the at least one multilayer structure. The first printed circuit board has a first surface and a first plurality of components mounted on the first surface. The first plurality of components is in electrical communication with the electrical contacts. The module further includes a second printed circuit board coupled to the at least one multilayer structure. The second printed circuit board has a second surface and a second plurality of components mounted on the second surface. The second plurality of components is in electrical communication with the electrical contacts. The second surface of the second printed circuit board faces the first surface of the first printed circuit board. The module further includes at least one thermally conductive layer positioned between the first plurality of components and the second plurality of components. The at least one thermally conductive layer is in thermal communication with the first plurality of components, the second plurality of components, and the electrical contacts.

Abstract translation: 模块可电连接到计算机系统。 模块包括至少一个多层结构，其具有可电连接到计算机系统的多个电触点。 该模块还包括耦合到至少一个多层结构的第一印刷电路板。 第一印刷电路板具有安装在第一表面上的第一表面和第一多个部件。 第一组多个组件与电触点电连通。 该模块还包括耦合到至少一个多层结构的第二印刷电路板。 第二印刷电路板具有安装在第二表面上的第二表面和第二多个部件。 第二组件与电触点电连通。 第二印刷电路板的第二表面面向第一印刷电路板的第一表面。 模块还包括位于第一多个部件和第二多个部件之间的至少一个导热层。 所述至少一个导热层与所述第一多个部件，所述第二多个部件和所述电触点热连通。

公开(公告)号：US08417870B2

公开(公告)日：2013-04-09

申请号：US12504131

申请日：2009-07-16

Applicant: Hyun Lee ,  Jayesh R. Bhakta

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F12/00 ,  G06F13/00

CPC classification number: G11C5/04 ,  G06F12/0623

Abstract: A load-reducing memory module includes a plurality of memory components such as DRAMs. The memory components are organized into sets or ranks such that they can be accessed simultaneously for the full data bit-width of the memory module. A plurality of load reducing switching circuits is used to drive data bits from a memory controller to the plurality of memory components. The load reducing switching circuits are also used to multiplex the data lines from the memory components and drive the data bits to the memory controller.

Abstract translation: 减载存储器模块包括诸如DRAM的多个存储器组件。 存储器组件被组织成集合或等级，使得它们可以被同时访问用于存储器模块的完整数据位宽。 多个负载降低开关电路用于将数据位从存储器控制器驱动到多个存储器组件。 负载降低开关电路还用于将来自存储器组件的数据线多路复用并将数据位驱动到存储器控制器。

公开(公告)号：US20110016269A1

公开(公告)日：2011-01-20

申请号：US12504131

申请日：2009-07-16

Applicant: Hyun Lee ,  Jayesh R. Bhakta

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F12/00

CPC classification number: G11C5/04 ,  G06F12/0623

Abstract: A load-reducing memory module includes a plurality of memory components such as DRAMs. The memory components are organized into sets or ranks such that they can be accessed simultaneously for the full data bit-width of the memory module. A plurality of load reducing switching circuits is used to drive data bits from a memory controller to the plurality of memory components. The load reducing switching circuits are also used to multiplex the data lines from the memory components and drive the data bits to the memory controller.

Abstract translation: 减载存储器模块包括诸如DRAM的多个存储器组件。 存储器组件被组织成集合或等级，使得它们可以被同时访问用于存储器模块的完整数据位宽。 多个负载降低开关电路用于将数据位从存储器控制器驱动到多个存储器组件。 负载降低开关电路还用于将来自存储器组件的数据线多路复用并将数据位驱动到存储器控制器。

公开(公告)号：US20110016250A1

公开(公告)日：2011-01-20

申请号：US12761179

申请日：2010-04-15

Applicant: Hyun Lee ,  Jayesh R. Bhakta

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F13/28 ,  G06F12/00 ,  G06F13/40

CPC classification number: G06F12/00 ,  G11C5/025 ,  G11C5/04 ,  G11C5/066 ,  G11C8/12

Abstract: A memory system and method utilizing one or more memory modules is provided. The memory module includes a plurality of memory devices and a controller configured to receive control information from a system memory controller and to produce module control signals. The memory module further includes a plurality of circuits, for example byte-wise buffers, which are configured to selectively isolate the plurality of memory devices from the system memory controller. The circuits are operable, in response to the module control signals, to drive write data from the system memory controller to the plurality of memory devices and to merge read data from the plurality of memory devices to the system memory controller. The circuits are distributed at corresponding positions separate from one another.

Abstract translation: 提供了利用一个或多个存储器模块的存储器系统和方法。 存储器模块包括多个存储器件和被配置为从系统存储器控制器接收控制信息并产生模块控制信号的控制器。 存储器模块还包括多个电路，例如逐字节缓冲器，其配置为将多个存储器设备与系统存储器控制器选择性地隔离。 响应于模块控制信号，这些电路可操作地将写数据从系统存储器控制器驱动到多个存储器装置，并将来自多个存储器件的读取数据合并到系统存储器控制器。 电路分布在彼此分开的相应位置。