公开(公告)号：US20060105530A1

公开(公告)日：2006-05-18

申请号：US10986692

申请日：2004-11-12

申请人： Chao-Sung Lai ,  Woei-Cherng Wu ,  Jer-Chyi Wang ,  Kung-Ming Fan ,  Shian-Jyh Lin

发明人： Chao-Sung Lai ,  Woei-Cherng Wu ,  Jer-Chyi Wang ,  Kung-Ming Fan ,  Shian-Jyh Lin

IPC分类号： H01L21/336

CPC分类号： H01L21/2822 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28238 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66575 ,  H01L29/78

摘要： A method for fabricating a semiconductor device with high-k materials. A high-k dielectric layer is formed on a substrate, followed by a fluorine-containing treatment of the high-k dielectric layer, forming an interface containing Si—F bonds.

摘要翻译： 一种制造具有高k材料的半导体器件的方法。 在基板上形成高k电介质层，接着对高k电介质层进行含氟处理，形成含有Si-F键的界面。

公开(公告)号：US07956403B2

公开(公告)日：2011-06-07

申请号：US12099168

申请日：2008-04-08

申请人： Ming-Cheng Chang ,  Wei-Ming Liao ,  Jer-Chyi Wang ,  Yi-Feng Chang

发明人： Ming-Cheng Chang ,  Wei-Ming Liao ,  Jer-Chyi Wang ,  Yi-Feng Chang

IPC分类号： H01L29/788

CPC分类号： H01L29/7887 ,  H01L21/28273 ,  H01L29/42336

摘要： A flash memory includes a substrate with a protrusion, a control gate, two floating gates, and a dielectric layer. The protrusion extends from a top face of the substrate. The control gate is formed on the protrusion of the substrate and extendedly covers opposite sidewalls of the protrusion. The floating gates are respectively formed on top of the protrusion and being on two opposite sides of the control gate. The dielectric layer is sandwiched the control gate and each of the two floating gates. Because of the arcuate control gate used in the flash memory, the controllability of the control gate is increased and the memory cell window is enhanced.

摘要翻译： 闪存包括具有突起的基板，控制栅极，两个浮动栅极和介电层。 突出部从基板的顶面延伸。 控制栅极形成在基板的突起上并且延伸地覆盖突起的相对的侧壁。 浮动栅极分别形成在突起的顶部并且位于控制栅极的两个相对侧上。 电介质层夹在控制栅极和两个浮栅之中。 由于在闪速存储器中使用的弧形控制门，所以控制栅极的可控性增加并且存储单元窗口被增强。

公开(公告)号：US07667262B2

公开(公告)日：2010-02-23

申请号：US12139499

申请日：2008-06-15

申请人： Wei-Ming Liao ,  Jer-Chyi Wang

发明人： Wei-Ming Liao ,  Jer-Chyi Wang

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/1037 ,  H01L29/1041 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7887

摘要： A memory structure includes: a substrate; a control gate positioned on the substrate; floating gates positioned at two sides of the control gate, wherein the floating gates have a U-shaped bottom embedded in the substrate; a first dielectric layer positioned between the control gate and the substrate; a second dielectric layer positioned between the U-shaped bottom of the floating gates and the substrate; a third dielectric layer positioned between the control gate and the floating gates; a local doping region positioned around the floating gates channel; and a source/drain doping region positioned in the substrate at a side of the floating gates.

摘要翻译： 存储器结构包括：衬底; 位于所述基板上的控制门; 位于控制栅极两侧的浮动栅极，其中浮动栅极具有埋入基板中的U形底部; 位于所述控制栅极和所述衬底之间的第一电介质层; 位于浮置栅极的U形底部和衬底之间的第二电介质层; 位于所述控制栅极和所述浮动栅极之间的第三介电层; 位于浮动栅极通道周围的局部掺杂区域; 以及位于浮动栅极一侧的衬底中的源极/漏极掺杂区域。

公开(公告)号：US08343829B2

公开(公告)日：2013-01-01

申请号：US13171405

申请日：2011-06-28

申请人： Jer-Chyi Wang ,  Tieh-Chiang Wu ,  Chung-Yuan Lee ,  Jeng-Ping Lin

发明人： Jer-Chyi Wang ,  Tieh-Chiang Wu ,  Chung-Yuan Lee ,  Jeng-Ping Lin

IPC分类号： H01L21/8242 ,  H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66621

摘要： A recessed-gate transistor device includes a gate electrode embedded in a gate trench formed in a semiconductor substrate, wherein the gate trench includes a vertical sidewall and a U-shaped bottom. A source region is provided at one side of the gate trench within the semiconductor substrate. A drain region is provided at the other side thereof. An asymmetric gate dielectric layer is formed between the gate electrode and the semiconductor substrate. The asymmetric gate dielectric layer has a first thickness between the gate electrode and the drain region and a second thickness between the gate electrode and the source region, wherein the first thickness is thicker than the second thickness.

摘要翻译： 凹入栅极晶体管器件包括嵌入在半导体衬底中形成的栅极沟槽中的栅电极，其中栅极沟槽包括垂直侧壁和U形底部。 源区域设置在半导体衬底内的栅极沟槽的一侧。 漏极区域设置在其另一侧。 在栅电极和半导体衬底之间形成非对称栅介质层。 不对称栅极介电层在栅电极和漏极区之间具有第一厚度，并且在栅极和源极区之间具有第二厚度，其中第一厚度比第二厚度厚。

公开(公告)号：US20090256189A1

公开(公告)日：2009-10-15

申请号：US12139499

申请日：2008-06-15

申请人： Wei-Ming Liao ,  Jer-Chyi Wang

发明人： Wei-Ming Liao ,  Jer-Chyi Wang

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/1037 ,  H01L29/1041 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7887

摘要： A memory structure includes: a substrate; a control gate positioned on the substrate; floating gates positioned at two sides of the control gate, wherein the floating gates have a U-shaped bottom embedded in the substrate; a first dielectric layer positioned between the control gate and the substrate; a second dielectric layer positioned between the U-shaped bottom of the floating gates and the substrate; a third dielectric layer positioned between the control gate and the floating gates; a local doping region positioned around the floating gates channel; and a source/drain doping region positioned in the substrate at a side of the floating gates.

摘要翻译： 存储器结构包括：衬底; 位于所述基板上的控制门; 位于控制栅极两侧的浮动栅极，其中浮动栅极具有埋入基板中的U形底部; 位于所述控制栅极和所述衬底之间的第一电介质层; 位于浮置栅极的U形底部和衬底之间的第二电介质层; 位于所述控制栅极和所述浮动栅极之间的第三介电层; 位于浮动栅极通道周围的局部掺杂区域; 以及位于浮动栅极一侧的衬底中的源极/漏极掺杂区域。

公开(公告)号：US20090085089A1

公开(公告)日：2009-04-02

申请号：US12099168

申请日：2008-04-08

申请人： Ming-Cheng Chang ,  Wei-Ming Liao ,  Jer-Chyi Wang ,  Yi-Feng Chang

发明人： Ming-Cheng Chang ,  Wei-Ming Liao ,  Jer-Chyi Wang ,  Yi-Feng Chang

IPC分类号： H01L29/788

CPC分类号： H01L29/7887 ,  H01L21/28273 ,  H01L29/42336

摘要： A flash memory includes a substrate with a protrusion, a control gate, two floating gates, and a dielectric layer. The protrusion extends from a top face of the substrate. The control gate is formed on the protrusion of the substrate and extendedly covers opposite sidewalls of the protrusion. The floating gates are respectively formed on top of the protrusion and being on two opposite sides of the control gate. The dielectric layer is sandwiched the control gate and each of the two floating gates. Because of the arcuate control gate used in the flash memory, the controllability of the control gate is increased and the memory cell window is enhanced.

摘要翻译： 闪存包括具有突起的基板，控制栅极，两个浮动栅极和介电层。 突出部从基板的顶面延伸。 控制栅极形成在基板的突起上并且延伸地覆盖突起的相对的侧壁。 浮动栅极分别形成在突起的顶部并且位于控制栅极的两个相对侧上。 电介质层夹在控制栅极和两个浮栅之中。 由于在闪速存储器中使用的弧形控制门，所以控制栅极的可控性增加并且存储单元窗口被增强。