公开(公告)号：US06933782B1

公开(公告)日：2005-08-23

申请号：US10956966

申请日：2004-10-01

申请人： Jinghui Lu

发明人： Jinghui Lu

IPC分类号： H03L7/06 ,  H03M9/00 ,  H03F3/45

CPC分类号： H03M9/00 ,  H03L7/06

摘要： Described are high-speed parallel-to-serial converters. The converters include data combiners with differential current-steering circuits that respond to parallel data bits by producing complementary current signals representing a differential, serialized version of the parallel data bits. One embodiment includes inductive and resistive loads to equalize the gain over the frequency of interest to reduce data-deterministic jitter.

摘要翻译： 描述了高速并行到串行转换器。 转换器包括具有差分电流 - 转向电路的数据组合器，其通过产生表示并行数据位的差分串行版本的互补电流信号来响应并行数据位。 一个实施例包括电感和电阻负载以均衡感兴趣频率上的增益以减少数据确定性抖动。

公开(公告)号：US06864728B1

公开(公告)日：2005-03-08

申请号：US10377948

申请日：2003-02-28

申请人： Jinghui Lu

发明人： Jinghui Lu

IPC分类号： H03D7/14 ,  H03J3/20 ,  H03B19/00

CPC分类号： H03J3/20 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1475 ,  H03D7/1483 ,  H03D2200/0033

摘要： A frequency multiplier and amplification circuit are disclosed. One embodiment of the present invention comprises: a multiplier operably coupled to multiply a first sinusoidal waveform having a first frequency with a second sinusoidal waveform having a second frequency to produce a third sinusoidal waveform, having a frequency representative of a difference between the first frequency and the second frequency, and a fourth sinusoidal waveform having a frequency representative of a sum of the first and second frequencies; and a frequency-tuned load operably coupled to substantially attenuate the third sinusoidal waveform and to substantially pass the fourth sinusoidal waveform as an output of the frequency-tuned multiplier circuit. The frequency-tuned multiplier circuit can be a single-ended multiplier circuit or a differential multiplier circuit with corresponding single-ended or differential first and second sinusoidal waveforms.

摘要翻译： 公开了一种倍频器和放大电路。 本发明的一个实施例包括：乘法器，可操作地耦合以将具有第一频率的第一正弦波形与具有第二频率的第二正弦波形相乘以产生第三正弦波形，其具有代表第一频率和 第二频率和具有表示第一和第二频率之和的频率的第四正弦波形; 以及频率调谐负载，其可操作地耦合以基本上衰减所述第三正弦波形并且基本上将所述第四正弦波形作为所述频率调谐乘法器电路的输出。 频率调谐乘法器电路可以是具有对应的单端或差分第一和第二正弦波形的单端乘法器电路或差分乘法器电路。

公开(公告)号：US06765377B1

公开(公告)日：2004-07-20

申请号：US10043636

申请日：2002-01-09

申请人： Jinghui Lu

发明人： Jinghui Lu

IPC分类号： G01R3500

CPC分类号： H03F3/45188 ,  H03F1/42 ,  H03F2200/36 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45638 ,  H03F2203/45644 ,  H03F2203/45702

摘要： A buffer employs an input stage with an active, LC load. The active load includes integrated inductors that combine with the parasitic gate capacitances of a pair of transistors in a negative-transconductance (−Gm) booster configuration. The resulting active load emphasizes a desired frequency, improving the quality, or “Q,” of the input stage, and consequently of the entire buffer.

摘要翻译： 缓冲器采用具有有源LC负载的输入级。 有源负载包括与负跨导（-Gm）升压器配置中的一对晶体管的寄生栅极电容组合的集成电感器。 所产生的有效负载强调所需的频率，改善输入级的质量或“Q”，从而强调整个缓冲器的质量。

公开(公告)号：US06538499B1

公开(公告)日：2003-03-25

申请号：US10043717

申请日：2002-01-09

申请人： Jinghui Lu

发明人： Jinghui Lu

IPC分类号： H03L706

CPC分类号： H03L7/06 ,  H03H7/0115 ,  H03H7/175 ,  H03H11/1213

摘要： A post PLL filter is coupled to the output terminal of a phase locked loop. The post PLL filter reduces the jitter of the PLL output clock signal by increasing the Q of the phase locked loop. In addition, some embodiments of the present invention also provides amplitude magnification of the PLL output clock signal.

摘要翻译： 后PLL滤波器耦合到锁相环的输出端。 后PLL滤波器通过增加锁相环的Q来减少PLL输出时钟信号的抖动。 此外，本发明的一些实施例还提供PLL输出时钟信号的振幅放大率。

公开(公告)号：US06348817B2

公开(公告)日：2002-02-19

申请号：US09310771

申请日：1999-05-10

申请人： Jinghui Lu ,  Edward K. F. Lee

发明人： Jinghui Lu ,  Edward K. F. Lee

IPC分类号： H03B100

CPC分类号： H04L25/0282 ,  H03K17/04106 ,  H03K17/693 ,  H03K19/01831 ,  H04L25/0276 ,  H04L25/029

摘要： An integrated circuit driver provides, among other things, a high data communication rate, a large common mode output voltage range, avoidance of spikethrough current that increases power consumption, improved switching speed using current-steering techniques, and improved matching of steady-state output current in the high logic state to that of the low logic state. The driver includes complementary differential pairs and associated current mirror circuits that differentially source/sink current at a pair of load conductors to drive the load conductors into a logic state. A single-ended embodiment is also described.

摘要翻译： 集成电路驱动器提供了高数据通信速率，大的共模输出电压范围，避免了增加功耗的快速消耗电流，使用电流转向技术提高了开关速度，以及改进了稳态输出的匹配 处于高逻辑状态的电流为低逻辑状态。 驱动器包括互补差分对和相关联的电流镜电路，其在一对负载导体处差分地源/吸收电流以驱动负载导体进入逻辑状态。 还描述了单端实施例。

公开(公告)号：US07876844B2

公开(公告)日：2011-01-25

申请号：US12023034

申请日：2008-01-31

申请人： JingHui Lu

发明人： JingHui Lu

IPC分类号： H04K1/10 ,  H04L27/28

CPC分类号： H04L27/2647 ,  H04L5/0048 ,  H04L5/005 ,  H04L27/2659

摘要： Techniques for determining positions of pilot sub-carriers in a received OFDM symbol are described. Components of pilot sub-carriers from a theoretical OFDM symbol are extracted to form M theoretical pilot sequences according to M possible distributions in frequency domain of the pilot sub-carriers in the theoretical OFDM symbol. Components of pilot sub-carriers from the received OFDM symbol are also extracted to form K hypothetical pilot sequences according to K possible distributions in frequency domain of pilot sub-carriers in the received OFDM symbol. The correlations of every two adjacent elements of the theoretical pilot sequences are calculated to get M corresponding theoretical correlation sequences, and the correlations of every two adjacent elements of the hypothetical pilot sequence are also calculated to get K corresponding hypothetical correlation sequences. Sequence correlations between the hypothetical correlation sequences and the theoretical correlation sequences are then calculated. The positions of pilot sub-carriers in the received OFDM symbol can be determined from the one that has the maximum modulus value.

摘要翻译： 描述用于确定接收的OFDM符号中的导频子载波的位置的技术。 提取来自理论OFDM符号的导频子载波的组成部分，以根据理论OFDM符号中的导频子载波的频域中的M个可能分布形成M个理论导频序列。 根据所接收的OFDM符号中的导频子载波的频域中的K个可能分布，也提取来自接收到的OFDM符号的导频子载波的组成部分，形成K个假想导频序列。 计算理论导频序列的每两个相邻元素的相关性以得到M个对应的理论相关序列，并且还计算假设导频序列的每两个相邻元素的相关性以获得K个相应的假设相关序列。 然后计算假设相关序列与理论相关序列之间的序列相关性。 可以从具有最大模数值的导频子载波中确定接收的OFDM符号中的导频子载波的位置。

公开(公告)号：US07523215B1

公开(公告)日：2009-04-21

申请号：US10047195

申请日：2002-01-14

申请人： Moises E. Robinson ,  Shahriar Rokhsaz ,  Jinghui Lu

发明人： Moises E. Robinson ,  Shahriar Rokhsaz ,  Jinghui Lu

IPC分类号： G06F15/16

CPC分类号： H04L69/24

摘要： A method and apparatus for a transmitting entity within a micro-area network to establish a data transmission within the network includes processing that begins by determining the identity of a target entity within the micro-area network. The processing then continues by determining transmission characteristics of at least one communication path between the transmitting entity and target entity of the micro-area network. The processing then continues by determining a transmission convention based on the transmission characteristics. The processing then continues by providing the transmission convention to the target entity.

摘要翻译： 用于在微区域网内发送实体以建立网络内的数据传输的方法和装置包括通过确定微区域网内的目标实体的身份开始的处理。 然后通过确定微区域网络的发送实体和目标实体之间的至少一个通信路径的传输特性来继续处理。 然后通过基于传输特性确定传输约定来继续处理。 然后通过向目标实体提供传输约定来继续处理。

公开(公告)号：US07058120B1

公开(公告)日：2006-06-06

申请号：US10051222

申请日：2002-01-18

申请人： Jinghui Lu ,  Shahriar Rokhsaz ,  Stephen D. Anderson ,  Michael A. Nix ,  Ahmed Younis ,  Michael Ren Kent ,  Yvette P. Lee ,  Firas N. Abughazaleh ,  Brian T. Brunn ,  Moises E. Robinson ,  Kazi S. Hossain

发明人： Jinghui Lu ,  Shahriar Rokhsaz ,  Stephen D. Anderson ,  Michael A. Nix ,  Ahmed Younis ,  Michael Ren Kent ,  Yvette P. Lee ,  Firas N. Abughazaleh ,  Brian T. Brunn ,  Moises E. Robinson ,  Kazi S. Hossain

IPC分类号： H03K11/00 ,  H04L25/60 ,  H04L25/64

CPC分类号： H03L7/093 ,  H03K5/1565 ,  H03M9/00 ,  H04L7/0004 ,  H04L7/033 ,  H04W4/18

摘要： A transceiver includes a receiver section and a transmitter section. The receiver section includes a clocking circuit, a serial-to-parallel module, and compensation. The transmitter section includes a clocking circuit, parallel-to-serial module, and compensation. The compensation within the receiver section and transmitter section compensates for integrated circuit (IC) processing limits and/or integrated circuit (IC) fabrication limits within the clocking circuits, serial-to-parallel module, and parallel-to-serial module that would otherwise limit the speed at which the transceiver could transport data.

摘要翻译： 收发机包括接收机部分和发射机部分。 接收器部分包括时钟电路，串行到并行模块和补偿。 发射机部分包括时钟电路，并行到串行模块和补偿。 接收器部分和发射器部分内的补偿补偿了时钟控制电路，串行到并行模块和并行到串行模块的集成电路（IC）处理限制和/或集成电路（IC）制造限制，否则 限制收发器可以传输数据的速度。

公开(公告)号：US06946849B1

公开(公告)日：2005-09-20

申请号：US10869010

申请日：2004-06-15

申请人： Jinghui Lu

发明人： Jinghui Lu

IPC分类号： H03F1/42 ,  H03F3/45 ,  G01R35/00

CPC分类号： H03F3/45188 ,  H03F1/42 ,  H03F2200/36 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45638 ,  H03F2203/45644 ,  H03F2203/45702

摘要： A circuit for calibrating a resistance between a first circuit node and a second circuit node is disclosed. The circuit comprises a reference resistor connected between first and second reference nodes; a first transistor having a first current-handling terminal connected to the first reference node, a second current-handling terminal, and a first control terminal; and a second transistor having a third current-handling terminal connected to the first circuit node, a fourth current-handling terminal connected to the second circuit node, and a second control terminal connected to the first control terminal.

摘要翻译： 公开了一种用于校准第一电路节点和第二电路节点之间的电阻的电路。 电路包括连接在第一和第二参考节点之间的参考电阻器; 具有连接到第一参考节点的第一电流处理终端的第一晶体管，第二电流处理终端和第一控制端; 以及具有连接到第一电路节点的第三电流处理终端的第二晶体管，连接到第二电路节点的第四电流处理终端和连接到第一控制端的第二控制端。

公开(公告)号：US20100124277A1

公开(公告)日：2010-05-20

申请号：US12475524

申请日：2009-05-31

申请人： Hao Wang ,  Song Qiu ,  Jinghui Lu

发明人： Hao Wang ,  Song Qiu ,  Jinghui Lu

IPC分类号： H04N7/12

CPC分类号： H04N19/17 ,  H04N19/107 ,  H04N19/132 ,  H04N19/172

摘要： A video encoding technique producing an even output bit stream is disclosed. According to one aspect of the present invention, an instantaneous peak of the output bit stream is greatly reduced by dividing one image frame into a key area and a background area, then inter-frame encoding the key area and the background area in different frames respectively. In other words, a whole bit stream of one I frame in the prior art is distributed into two or more image frames in the present invention.

摘要翻译： 公开了产生偶数输出比特流的视频编码技术。 根据本发明的一个方面，通过将一个图像帧分成关键区域和背景区域，输出比特流的瞬时峰值被大大减小，然后分别对不同帧中的关键区域和背景区域进行帧间编码 。 换句话说，在本发明中，现有技术中的一个I帧的整个比特流被分配到两个或更多个图像帧中。