公开(公告)号：US20080307170A1

公开(公告)日：2008-12-11

申请号：US12013845

申请日：2008-01-14

Applicant: Joong-Ho Lee

Inventor： Joong-Ho Lee

IPC: G06F12/00

CPC classification number: G11C5/02

Abstract: A memory module includes a plurality of ranks that each include a first pin group and a second pin group for receiving external pin signals, and a rank selecting unit included in each of the plurality of ranks, the rank selecting unit configured to output different rank pin signals to each rank by using signals of the first pin group.

Abstract translation: 存储器模块包括多个排列，每个排列包括用于接收外部引脚信号的第一引脚组和第二引脚组，以及包括在多个等级的每一个中的等级选择单元，所述等级选择单元被配置为输出不同的等级引脚 通过使用第一引脚组的信号将信号发送到每个等级。

公开(公告)号：US08184165B2

公开(公告)日：2012-05-22

申请号：US12274648

申请日：2008-11-20

Applicant: Il-Seob Baek ,  Seung-Jun Lee ,  Joong-Ho Lee

Inventor： Il-Seob Baek ,  Seung-Jun Lee ,  Joong-Ho Lee

IPC: H04N5/225

CPC classification number: H04N5/232

Abstract: An apparatus and method for separating and connecting a main camera and a sub camera in a portable terminal are provided. The portable terminal includes a main camera for receiving a main clock signal from a main chip and transmitting a main camera pixel clock signal to the main chip in response to the main clock signal, a sub camera for receiving the main clock signal from the main chip and transmitting a sub camera pixel clock signal to the main chip in response to the main clock signal, and a switch for configuring a path from the main chip to at least one of the main camera and the sub camera.

Abstract translation: 提供了一种用于在便携式终端中分离和连接主摄像机和子摄像机的装置和方法。 便携式终端包括用于从主芯片接收主时钟信号并且响应于主时钟信号将主相机像素时钟信号发送到主芯片的主相机，用于从主芯片接收主时钟信号的副相机 以及响应于所述主时钟信号将副相机像素时钟信号发送到所述主芯片，以及用于配置从所述主芯片到所述主相机和所述副相机中的至少一个的路径的开关。

公开(公告)号：US20120110398A1

公开(公告)日：2012-05-03

申请号：US12970869

申请日：2010-12-16

Applicant: Joong Ho LEE

Inventor： Joong Ho LEE

IPC: G11C29/04 ,  G06F11/22

CPC classification number: G06F11/1004 ,  G11C2029/0411

Abstract: Various embodiments of a memory system are disclosed. In one exemplary embodiment, the memory system may include a semiconductor memory apparatus configured to generate error check signals in a column direction and a row direction of data groups to be transmitted through a plurality of data input/output terminals in a read operation and output the error check signals together with the data groups, and a memory controller configured to control data read/write operations of the semiconductor memory apparatus, generate error check signals by performing error check in a column direction and a row direction of data groups to be transmitted in a write operation, and provide the error check signals to the semiconductor memory apparatus together with the data groups.

Abstract translation: 公开了存储器系统的各种实施例。 在一个示例性实施例中，存储器系统可以包括：半导体存储器装置，被配置为在读取操作中通过多个数据输入/输出端子发送的数据组的列方向和行方向产生错误校验信号，并输出 错误检查信号与数据组一起，以及存储器控制器，被配置为控制半导体存储器件的数据读/写操作，通过在要发送的数据组的列方向和行方向上执行错误校验来生成错误校验信号 写操作，并且与数据组一起向半导体存储装置提供错误检查信号。

公开(公告)号：US08050127B2

公开(公告)日：2011-11-01

申请号：US12494844

申请日：2009-06-30

Applicant: Joong-Ho Lee

Inventor： Joong-Ho Lee

IPC: G11C7/02

CPC classification number: G11C11/4097 ,  G11C7/02 ,  G11C7/1066 ,  G11C7/18 ,  G11C2207/005

Abstract: A semiconductor memory device includes first and second sub-memory-cell areas configured to form a memory cell matrix and include a first bit line and a second bit line respectively to form a data transfer path corresponding to a predetermined memory cell, an additional bit line configured to cross the first sub-memory-cell area and form a data transfer path by being connected with the second bit line and a sensing and amplifying unit configured to sense and amplify data inputted through the additional bit line and the first bit line.

Abstract translation: 半导体存储器件包括被配置为形成存储单元矩阵并且分别包括第一位线和第二位线的第一和第二子存储器单元区域，以形成对应于预定存储器单元的数据传输路径，附加位线 被配置为跨越第一子存储单元区域并通过与第二位线连接形成数据传送路径;感测和放大单元，被配置为感测和放大通过附加位线和第一位线输入的数据。

公开(公告)号：US20110242056A1

公开(公告)日：2011-10-06

申请号：US13125553

申请日：2008-12-30

Applicant: Joong Ho Lee ,  Ji Hyung Park ,  Ki Won Yeom

Inventor： Joong Ho Lee ,  Ji Hyung Park ,  Ki Won Yeom

IPC: G06F3/042

CPC classification number: G06F3/0421 ,  G06F3/0418 ,  G06F2203/04104

Abstract: Disclosed is an optical recognition user input device and method for recognizing user input that can prevent an error in recognition of plural touch points. A plurality of optical transmission/reception modules (T/R) are disposed around a touch panel including a plurality of pixels. Each of the optical T/R modules includes a light emitting unit and a light receiving unit. A controller controls operation of the optical T/R modules and calculates a user touch location on the touch panel based on an optical signal received by the light receiving unit.

Abstract translation: 公开了一种用于识别可以防止识别多个接触点的错误的用户输入的光学识别用户输入装置和方法。 多个光发送/接收模块（T / R）设置在包括多个像素的触摸面板周围。 每个光学T / R模块包括发光单元和光接收单元。 控制器控制光学T / R模块的操作，并且基于由光接收单元接收的光信号来计算触摸面板上的用户触摸位置。

公开(公告)号：US08000158B2

公开(公告)日：2011-08-16

申请号：US12490690

申请日：2009-06-24

Applicant: Joong-Ho Lee

Inventor： Joong-Ho Lee

IPC: G11C7/00

CPC classification number: G11C29/838 ,  G11C29/24 ,  G11C29/816

Abstract: A semiconductor memory device includes a plurality of memory cell matrixes each of which contains plural memory cell arrays whose number is lager than 2n and smaller than 2n+1, n being a natural number. The semiconductor memory device includes normal memory cell arrays including 2m numbers of memory cell arrays of the plurality of memory cell matrixes, m being a bit of addresses, wherein a data access operation is performed on normal memory cells in the normal memory cell arrays as normal word lines corresponding to the normal memory cells are activated in response to the addresses, and additional redundancy memory cell arrays in the plurality of memory cell matrixes, wherein repair-expected memory cells in the normal memory cell arrays are replaced with the additional redundancy memory cell arrays as redundancy word lines corresponding to the additional redundancy memory cells are activated in response to the addresses corresponding to the repair-expected memory cells.

Abstract translation: 半导体存储器件包括多个存储单元矩阵，每个存储单元矩阵包含多于2n并且小于2n + 1的多个存储单元阵列，n是自然数。 半导体存储器件包括包括多个存储单元矩阵的2m个存储单元阵列的正常存储单元阵列，m是地址位，其中在正常存储单元阵列中的正常存储单元上执行数据访问操作，如正常 对应于正常存储器单元的字线响应于地址被激活，并且多个存储单元矩阵中的附加冗余存储单元阵列，其中正常存储器单元阵列中的修复预期存储单元被替换为附加冗余存储单元 对应于附加冗余存储单元的冗余字线的阵列响应于对应于修复预期存储单元的地址被激活。

公开(公告)号：US20090083234A1

公开(公告)日：2009-03-26

申请号：US12282824

申请日：2006-03-14

Applicant: Ki Won Yeom ,  Ji Hyung Park ,  Joong Ho Lee ,  Seung Soo Lee ,  Ju Il Eom

Inventor： Ki Won Yeom ,  Ji Hyung Park ,  Joong Ho Lee ,  Seung Soo Lee ,  Ju Il Eom

IPC: G06F7/06 ,  G06F17/30

CPC classification number: H04L12/12 ,  H04L67/14 ,  H04L69/18 ,  Y02D50/40

Abstract: An intelligent computing device agent system for auto recognition of a computing environment of multi-user and optimum information exchange configuration is provided. In the computing device agent system automatically detects the user's computing environment and intelligently makes network access configuration and an information exchange type required between interacting computing devices identical to each other, so that fast, convenient interaction is carried out without complex network configuring or multi-step environment configuring for information exchange.

Abstract translation: 提供了一种用于自动识别多用户和最佳信息交换配置的计算环境的智能计算设备代理系统。 在计算设备代理系统中，自动检测用户的计算环境，智能地使交互式计算设备之间的网络访问配置和信息交换类型相互相同，从而实现快速，方便的交互，无需复杂的网络配置或多步骤 环境配置信息交换。

公开(公告)号：US07230865B2

公开(公告)日：2007-06-12

申请号：US11321518

申请日：2005-12-30

Applicant: Joong Ho Lee

Inventor： Joong Ho Lee

IPC: G11C7/00

CPC classification number: G11C29/48 ,  G11C29/1201 ,  G11C29/46

Abstract: Provided is an input/output line sharing apparatus of a semiconductor memory device. In this apparatus, a global input/output line is shared by a data line signal and a test mode signal, and an input/output line between test mode signals is shared. The apparatus comprises a global input/output line, a first control signal generating unit configured to generate a test mode control signal from a test mode register set signal, a multiplexer configured to output a signal selected from a data line signal and a test mode signal to the global input/output line in response to the test mode control signal, and a latch unit configured to store the test mode signal outputted from the global input/output line in response to the test mode control signal.

Abstract translation: 提供一种半导体存储器件的输入/输出线共享装置。 在该装置中，全局输入/输出线由数据线信号和测试模式信号共享，并且共用测试模式信号之间的输入/输出线。 该装置包括全局输入/输出线，第一控制信号产生单元，被配置为从测试模式寄存器设置信号产生测试模式控制信号;多路复用器，被配置为输出从数据线信号和测试模式信号中选出的信号 响应于测试模式控制信号到全局输入/输出线，以及锁存单元，被配置为存储响应于测试模式控制信号从全局输入/输出线输出的测试模式信号。

公开(公告)号：US20050242855A1

公开(公告)日：2005-11-03

申请号：US11086054

申请日：2005-03-22

Applicant: Joong Ho Lee

Inventor： Joong Ho Lee

IPC: G11C8/00 ,  H03L7/06 ,  H03L7/07 ,  H03L7/081

CPC classification number: H03L7/07 ,  H03L7/0814 ,  H03L7/0818

Abstract: Disclosed is a delay locked loop circuit (DLL) used for DDR SDRAM. The DLL provides a fast locking function. In particular, the DLL detects the level of a frequency and performs the fast locking function, thereby realizing a high integrated memory device having a reduced area of a delay part used in order to synchronize a phase of an external clock signal with a phase of an internal clock.

Abstract translation: 公开了用于DDR SDRAM的延迟锁定环电路（DLL）。 DLL提供快速锁定功能。 特别地，DLL检测频率的电平并执行快速锁定功能，从而实现具有减小的延迟部分的面积的高集成存储器件，以使外部时钟信号的相位与 内部时钟

公开(公告)号：US09395906B2

公开(公告)日：2016-07-19

申请号：US12188237

申请日：2008-08-08

Applicant: Seung Soo Lee ,  Ju Il Eom ,  Ki Won Yeom ,  Joong Ho Lee ,  Ji Hyung Park

Inventor： Seung Soo Lee ,  Ju Il Eom ,  Ki Won Yeom ,  Joong Ho Lee ,  Ji Hyung Park

IPC: G06F3/0488 ,  G06F3/0482

CPC classification number: G06F3/04883 ,  G06F3/0482

Abstract: A graphic user interface, an input/output computing apparatus for intuitive interfacing, and a method of interfacing are disclosed. The input/output computing apparatus for intuitive interfacing with a user, includes an input unit to detect one of a plurality of predetermined motions of the user and generate a signal corresponding to the detected predetermined motion, and a controller to carry out an operation corresponding to the signal and generate a control signal to display the result corresponding to the operation.

Abstract translation: 公开了一种图形用户接口，用于直观接口的输入/输出计算装置和接口方法。 用于与用户直观接口的输入/输出计算装置包括：输入单元，用于检测用户的多个预定运动中的一个，并产生对应于检测到的预定运动的信号;以及控制器，执行与 信号并产生一个控制信号，显示对应于该操作的结果。