公开(公告)号：US5812478A

公开(公告)日：1998-09-22

申请号：US651418

申请日：1996-05-22

申请人： Junichi Okamura

发明人： Junichi Okamura

IPC分类号： G11C5/02 ,  G11C7/10 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C7/1006 ,  G11C5/025 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1078

摘要： A semiconductor memory including first, second, and third data busses, and first and second memory cell arrays arranged among the first, second, and third data busses. During operation of the semiconductor memory, a first, a second, and a third circuit selectively couple the first, second, and third data busses to a fourth and a fifth data bus. Additionally, there is provided first and second buffer circuits, which are respectively coupled to the fourth and the fifth data busses, and a sixth data bus, which is commonly coupled to the first and second buffer circuits. A control circuit is used to control the operation of the switch circuits. In preferred embodiments, the number of buffer circuits in the semiconductor memory is less than or equal to the number of memory cell arrays.

摘要翻译： 包括第一，第二和第三数据总线的半导体存储器以及布置在第一，第二和第三数据总线之间的第一和第二存储单元阵列。 在半导体存储器的操作期间，第一，第二和第三电路将第一，第二和第三数据总线选择性地耦合到第四和第五数据总线。 另外，提供分别耦合到第四和第五数据总线的第一和第二缓冲电路，以及共同耦合到第一和第二缓冲电路的第六数据总线。 控制电路用于控制开关电路的工作。 在优选实施例中，半导体存储器中的缓冲电路的数量小于或等于存储单元阵列的数量。

公开(公告)号：US5673229A

公开(公告)日：1997-09-30

申请号：US612759

申请日：1996-03-08

申请人： Junichi Okamura ,  Tohru Furuyama

发明人： Junichi Okamura ,  Tohru Furuyama

IPC分类号： G01R31/28 ,  G01R31/30 ,  G11C8/12 ,  G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C29/00 ,  G11C29/06 ,  G11C29/34 ,  G11C29/50 ,  H01L21/66 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4085 ,  G11C11/4087 ,  G11C29/50 ,  G11C8/12 ,  G11C11/401

摘要： A dynamic random access memory includes a dynamic memory cell having a transfer N-channel MOS transistor and a capacitive element for storing data which is connected to the transfer N-channel MOS transistor, a word line connected to a gate of the transfer N-channel transistor, of the dynamic memory cell, and a word line driving voltage source, to which power voltage is input for raising the input power voltage to generate a word line driving voltage. Also, the dynamic random access memory includes an address circuit for generating internal address signals in accordance with externally input address signals, a word line selecting circuit for decoding the internal address signals and outputting a word line selecting signal which varies within a range between the word line driving voltage and a ground potential, and a word line driving circuit for driving a corresponding word line in accordance with the word line selecting signal, the word line driving circuit being provided in correspondence with the word line and having a P-channel MOS transistor which has a source connected to a first node having the word line driving voltage, a drain connected to the word line and a gate to which the word line selecting signal is applied.

摘要翻译： 动态随机存取存储器包括具有传输N沟道MOS晶体管的动态存储单元和用于存储连接到传输N沟道MOS晶体管的数据的电容元件，连接到传输N沟道的栅极的字线 晶体管，以及字线驱动电压源，输入电源电压以提高输入电源电压以产生字线驱动电压。 此外，动态随机存取存储器包括用于根据外部输入的地址信号产生内部地址信号的地址电路，用于对内部地址信号进行解码的字线选择电路，并输出在字之间的范围内变化的字线选择信号 线驱动电压和接地电位，以及用于根据字线选择信号驱动相应字线的字线驱动电路，字线驱动电路与字线对应地设置，并具有P沟道MOS晶体管 其源极连接到具有字线驱动电压的第一节点，连接到字线的漏极和施加了字线选择信号的栅极。

公开(公告)号：US09956633B2

公开(公告)日：2018-05-01

申请号：US13527532

申请日：2012-06-19

申请人： Akira Takaguchi ,  Issaku Sato ,  Noboru Hashimoto ,  Junichi Okamura

发明人： Akira Takaguchi ,  Issaku Sato ,  Noboru Hashimoto ,  Junichi Okamura

IPC分类号： B23K1/00 ,  B23K3/00 ,  B23K3/06

CPC分类号： B23K3/0653

摘要： A wave soldering tank includes a soldering tank body for housing molten solder and a solder feed chamber disposed within the soldering tank body. An axial-flow, multiple-blade screw-type pump is disposed so as to draw molten solder into the solder feed chamber through an inlet and discharge the molten solder through an outlet. In a preferred embodiment, the pump includes a rotatable hub and a plurality of helical blades secured to the hub at equal intervals in the circumferential direction of the hub, each of the blades overlapping an adjoining one of the blades when the blades are viewed in the axial direction of the impeller.

公开(公告)号：US20120255987A1

公开(公告)日：2012-10-11

申请号：US13527532

申请日：2012-06-19

申请人： Akira Takaguchi ,  Issaku Sato ,  Noboru Hashimoto ,  Junichi Okamura

发明人： Akira Takaguchi ,  Issaku Sato ,  Noboru Hashimoto ,  Junichi Okamura

IPC分类号： B23K3/06

CPC分类号： B23K3/0653

摘要： A wave soldering tank includes a soldering tank body for housing molten solder and a solder feed chamber disposed within the soldering tank body. An axial-flow, multiple-blade screw-type pump is disposed so as to draw molten solder into the solder feed chamber through an inlet and discharge the molten solder through an outlet. In a preferred embodiment, the pump includes a rotatable hub and a plurality of helical blades secured to the hub at equal intervals in the circumferential direction of the hub, each of the blades overlapping an adjoining one of the blades when the blades are viewed in the axial direction of the impeller.

摘要翻译： 波峰焊槽包括用于容纳熔融焊料的焊料槽体和设置在焊料槽体内的焊料供给室。 设置有轴向流动的多叶片螺杆式泵，以便通过入口将熔融焊料吸入焊料进料室，并通过出口排出熔融焊料。 在优选实施例中，泵包括可旋转轮毂和多个螺旋叶片，其在轮毂的圆周方向上以相等的间隔固定到轮毂，当在叶片中看到叶片时，每个叶片与相邻的叶片重叠 叶轮的轴向。

公开(公告)号：US08215534B2

公开(公告)日：2012-07-10

申请号：US10573449

申请日：2004-10-08

申请人： Akira Takaguchi ,  Issaku Sato ,  Noboru Hashimoto ,  Junichi Okamura

发明人： Akira Takaguchi ,  Issaku Sato ,  Noboru Hashimoto ,  Junichi Okamura

IPC分类号： B23K1/00 ,  B23K31/02

CPC分类号： B23K3/0653

摘要： A wave soldering tank includes a soldering tank body for housing molten solder and a solder feed chamber disposed within the soldering tank body. An axial-flow, multiple-blade screw-type pump is disposed so as to draw molten solder into the solder feed chamber through an inlet and discharge the molten solder through an outlet. In a preferred embodiment, the pump includes a rotatable hub and a plurality of helical blades secured to the hub at equal intervals in the circumferential direction of the hub, each of the blades overlapping an adjoining one of the blades when the blades are viewed in the axial direction of the impeller.

摘要翻译： 波峰焊槽包括用于容纳熔融焊料的焊料槽体和设置在焊料槽体内的焊料供给室。 设置有轴向流动的多叶片螺杆式泵，以便通过入口将熔融焊料吸入焊料进料室，并通过出口排出熔融焊料。 在优选实施例中，泵包括可旋转轮毂和多个螺旋叶片，其在轮毂的圆周方向上以相等的间隔固定到轮毂，当在叶片中看到叶片时，每个叶片与相邻的叶片重叠 叶轮的轴向。

公开(公告)号：US06532167B2

公开(公告)日：2003-03-11

申请号：US09903731

申请日：2001-07-13

申请人： Tetsuya Kaneko ,  Junichi Okamura

发明人： Tetsuya Kaneko ,  Junichi Okamura

IPC分类号： G11C1124

CPC分类号： G11C7/06

摘要： A voltage generator for outputting an output voltage at an output terminal thereof includes a driver MOS transistor of a first conductivity type having a first end connected to said output terminal and a capacitor connected between the output terminal and a second voltage node. The capacitor comprises a plurality of trench capacitors formed in a semiconductor substrate.

公开(公告)号：US6101148A

公开(公告)日：2000-08-08

申请号：US907019

申请日：1997-08-06

申请人： Junichi Okamura ,  Tohru Furuyama

发明人： Junichi Okamura ,  Tohru Furuyama

IPC分类号： G01R31/28 ,  G01R31/30 ,  G11C8/12 ,  G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C29/00 ,  G11C29/06 ,  G11C29/34 ,  G11C29/50 ,  H01L21/66 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C8/00

CPC分类号： G11C11/4085 ,  G11C11/4087 ,  G11C29/50 ,  G11C8/12 ,  G11C11/401

摘要： A dynamic random access memory includes a dynamic memory cell having a transfer N-channel MOS transistor and a capacitive element for storing data which is connected to the transfer N-channel MOS transistor, a word line connected to a gate of the transfer N-channel transistor, of the dynamic memory cell, and a word line driving voltage source, to which power voltage is input for raising the input power voltage to generate a word line driving voltage. Also, the dynamic random access memory includes an address circuit for generating internal address signals in accordance with externally input address signals, a word line selecting circuit for decoding the internal address signals and outputting a word line selecting signal which varies within a range between the word line driving voltage and a ground potential, and a word line driving circuit for driving a corresponding word line in accordance with the word line selecting signal, the word line driving circuit being provided in correspondence with the word line and having a P-channel MOS transistor which has a source connected to a first node having the word line driving voltage, a drain connected to the word line and a gate to which the word line selecting signal is applied.

摘要翻译： 动态随机存取存储器包括具有传输N沟道MOS晶体管的动态存储单元和用于存储连接到传输N沟道MOS晶体管的数据的电容元件，连接到传输N沟道的栅极的字线 晶体管，以及字线驱动电压源，输入电源电压以提高输入电源电压以产生字线驱动电压。 此外，动态随机存取存储器包括用于根据外部输入的地址信号产生内部地址信号的地址电路，用于对内部地址信号进行解码的字线选择电路，并输出在字之间的范围内变化的字线选择信号 线驱动电压和接地电位，以及用于根据字线选择信号驱动相应字线的字线驱动电路，字线驱动电路与字线对应地设置，并具有P沟道MOS晶体管 其源极连接到具有字线驱动电压的第一节点，连接到字线的漏极和施加了字线选择信号的栅极。

公开(公告)号：US5894442A

公开(公告)日：1999-04-13

申请号：US805614

申请日：1997-02-26

申请人： Junichi Okamura

发明人： Junichi Okamura

IPC分类号： G11C11/409 ,  G11C7/12 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4094 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C11/4094

摘要： The present invention relates to a semiconductor memory device which, while preventing an operation error, achieves the shortening of a precharging time and, hence, further shortening of a cycle time of a memory operation. The equalizing control circuit includes a latch circuit. An equalizing control circuit receives a signal WLact and a signal X-ADR from a predecoder and outputs an equalizing signal EQS from these two signals. A latch circuit in the equalizing control circuit is set (the inactivation of an equalizing signal) by a signal X-ADR which is activated with an internal RAS signal and holds its state. The latch circuit is reset (the activation of the equalizing signal) by a signal corresponding to a word line active signal WLact with a word line inactivated. By doing so, it is possible to provide the equalizing control circuit not directly depending upon the internal RAS signal.

摘要翻译： 半导体存储装置技术领域本发明涉及一种半导体存储装置，其在防止操作错误的同时，实现了预充电时间的缩短，从而进一步缩短了存储器操作的周期时间。 均衡控制电路包括锁存电路。 均衡控制电路从预解码器接收信号WLact和信号X-ADR，并从这两个信号输出均衡信号EQS。 通过用内部RAS信号激活的信号X-ADR来设定均衡控制电路中的锁存电路（均衡信号的失活）并保持其状态。 锁存电路通过与字线有效信号WLact相对应的信号复位（均衡信号的激活），字线失活。 通过这样做，可以根据内部RAS信号直接提供均衡控制电路。

公开(公告)号：US5625599A

公开(公告)日：1997-04-29

申请号：US548386

申请日：1995-10-26

申请人： Junichi Okamura

发明人： Junichi Okamura

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C11/401 ,  G11C11/4091 ,  G11C11/419 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C7/065 ,  G11C11/4091

摘要： In a DRAM or similar memory having sense amplifiers coupled to memory cells, a sense amplifier is switchably connected to a discharge circuit to discharge the terminal of the sense amplifier at high speed. The node of the sense amplifier is also coupled to a discharge circuit which discharges the node at a slower speed. In operation, only the node of a selected sense amplifier is discharged at high speed, while other non-selected sense amplifiers are activated by discharging the sense amplifier node at a lower speed. This mode of operation allows for the high speed activation of the selected sense amplifier with the associated current consumption being limited to that necessary to discharge the individual sense amplifier selected. The two discharge circuits may be two N channel MOS transistors connecting the node of the sense amplifier to two drive lines driven by independent circuits. The higher speed discharge circuit is implemented as an N channel MOS transistor which is switched by a signal from the column select line.

摘要翻译： 在具有耦合到存储单元的感测放大器的DRAM或类似存储器中，读出放大器可切换地连接到放电电路，以高速放电读出放大器的端子。 读出放大器的节点还耦合到放电电路，其以较慢的速度放电节点。 在操作中，只有所选择的读出放大器的节点以高速放电，而其他未选择的读出放大器通过以较低的速度放电读出放大器节点来激活。 这种操作模式允许所选择的读出放大器的高速激活，相关联的电流消耗被限制为放电所选择的各个读出放大器所必需的电流消耗。 两个放电电路可以是将感测放大器的节点连接到由独立电路驱动的两个驱动线的两个N沟道MOS晶体管。 高速放电电路被实现为通过来自列选择线的信号切换的N沟道MOS晶体管。

公开(公告)号：US20090110217A1

公开(公告)日：2009-04-30

申请号：US12285323

申请日：2008-10-01

申请人： Akira Yasuda ,  Junichi Okamura

发明人： Akira Yasuda ,  Junichi Okamura

IPC分类号： H03F99/00

CPC分类号： H04R3/08 ,  H03G3/20 ,  H03H15/00 ,  H03M3/344 ,  H03M3/414 ,  H03M3/504 ,  H03M7/3022 ,  H04R1/005 ,  H04R3/00 ,  H04R17/005

摘要： A digital/analog conversion apparatus for converting a digital signal into an analog signal. The digital/analog conversion apparatus can generate a high-quality analog signal, even when elements configuring the digital/analog conversion apparatus have variance, with high resolution and a small circuit size. The data conversion apparatus is provided with a first data converter for reducing the number of bits of an input signal, a second data converter for converting the format of the first output signal, and a third data converter for conversion into a code which corresponds to the history of the output from the second data converter.

摘要翻译： 一种用于将数字信号转换成模拟信号的数字/模拟转换装置。 即使构成数/模转换装置的元件具有高分辨率和小电路尺寸的差异，数/模转换装置也可以产生高质量的模拟信号。 数据转换装置设置有用于减少输入信号的位数的第一数据转换器，用于转换第一输出信号的格式的第二数据转换器和用于转换成与第一输出信号对应的代码的第三数据转换器 来自第二个数据转换器的输出历史。