公开(公告)号：US07584434B2

公开(公告)日：2009-09-01

申请号：US10200129

申请日：2002-07-23

申请人： Junichi Okamura

发明人： Junichi Okamura

IPC分类号： G06F3/00 ,  G06F3/14

CPC分类号： G06F17/30899 ,  G09G2340/145 ,  Y10S707/99945 ,  Y10S707/99948

摘要： A map database site S comprises a map information database Sb for accumulating the map data constructed of units for displaying of unit images m each having a display range smaller than a display range of a map image M corresponding to one page of a map image displayed on a user terminal T, in association with position data indicating the display ranges of the individual unit images m. A user terminal T comprises map-image display means for combining the map data of a plurality of units with each other on the basis of the associated position data, which are read out from the map information database Sb provided in the map database site S and transmitted from the map database site S, to form the one-page map image M for display.

摘要翻译： 地图数据库站点S包括地图信息数据库Sb，用于累积由显示范围小于对应于显示在其上的地图图像的一页的地图图像M的显示范围的单位图像m的显示单元构成的地图数据 用户终端T与指示各单位图像m的显示范围的位置数据相关联。 用户终端T包括地图图像显示装置，用于根据从地图数据库站点S中提供的地图信息数据库Sb中读出的关联位置数据来组合多个单元的地图数据;以及 从地图数据库站点S发送，形成用于显示的单页地图图像M.

公开(公告)号：US07129795B2

公开(公告)日：2006-10-31

申请号：US10488693

申请日：2001-09-12

申请人： Junichi Okamura

发明人： Junichi Okamura

IPC分类号： H03B27/00

CPC分类号： H03K5/1506 ,  H03K3/0322 ,  H03K5/133

摘要： A semiconductor integrated circuit in which, when leading out multiple-phase clock signal wirings from the ring oscillator circuit capable of oscillating at a high frequency, increase in the area of the substrate and deterioration in the clock phase accuracy caused by the non-uniform stray capacitances among the multiple-phase clock signal wirings are prevented. The semiconductor integrated circuit includes: N-stage amplifying circuits connected in a form of a ring to perform oscillating operation, which amplifying circuits are arranged in a semiconductor substrate to be divided into a plurality of rows, wherein in each row an amplifying circuit of “m−1”th stage and an amplifying circuit of “m”th stage are not adjacent to each other, where m is an arbitrary integer number within a range from 2 to N; and a plurality of wirings for respectively leading out a plurality of output signals from the amplifying circuits disposed in one of the plurality of rows.

摘要翻译： 一种半导体集成电路，其中当从能够以高频振荡的环形振荡器电路引出多相时钟信号布线时，衬底的面积增加并且由不均匀杂散引起的时钟相位精度的劣化 防止多相时钟信号布线之间的电容。 半导体集成电路包括：以环形连接的N级放大电路进行振荡动作，该放大电路配置在半导体衬底中，被分成多行，其中，在每行中，放大电路为“ m-1级和“m”级的放大电路彼此不相邻，其中m是在2至N的范围内的任意整数; 以及用于分别从布置在所述多行中的一行中的放大电路引出多个输出信号的多个布线。

公开(公告)号：US07043202B2

公开(公告)日：2006-05-09

申请号：US10537472

申请日：2003-12-08

申请人： Seiichi Ozawa ,  Junichi Okamura

发明人： Seiichi Ozawa ,  Junichi Okamura

IPC分类号： H04B7/165 ,  H04B1/00

CPC分类号： G06F1/08 ,  H03K3/0322 ,  H03L7/0996 ,  H03L7/18

摘要： A phase-selective type frequency modulator capable of easing the restriction on a phase range of a modulated clock signal. The phase-selective type frequency modulator includes a multiphase clock signal generating circuit 101 for generating N-phase clock signals; a control circuit 104 for sequentially activating one of first group of clock selection signals indicating a clock signal to be selected from the N-phase clock signals; an edge appearance time adjustment circuit 103 for adjusting a rising edge appearance time and/or a trailing edge appearance time of the first group of clock selection signals outputted from the control circuit 104 to output second group of clock selection signals; and a modulated clock signal generating circuit 102 for selecting one clock signal from the N-phase clock signals in accordance with an activated state of the second group of clock selection signals outputted from the edge appearance time adjustment circuit 103 to output a modulated clock signal MCK.

公开(公告)号：US20060025094A1

公开(公告)日：2006-02-02

申请号：US10537472

申请日：2003-12-08

申请人： Seiichi Ozawa ,  Junichi Okamura

发明人： Seiichi Ozawa ,  Junichi Okamura

IPC分类号： H04B1/16 ,  H04B1/06 ,  H04B7/00

CPC分类号： G06F1/08 ,  H03K3/0322 ,  H03L7/0996 ,  H03L7/18

摘要： A phase-selective type frequency modulator capable of easing the restriction on a phase range of a modulated clock signal. The phase-selective type frequency modulator includes a multiphase clock signal generating circuit 101 for generating N-phase clock signals; a control circuit 104 for sequentially activating one of first group of clock selection signals indicating a clock signal to be selected from the N-phase clock signals; an edge appearance time adjustment circuit 103 for adjusting a rising edge appearance time and/or a trailing edge appearance time of the first group of clock selection signals outputted from the control circuit 104 to output second group of clock selection signals; and a modulated clock signal generating circuit 102 for selecting one clock signal from the N-phase clock signals in accordance with an activated state of the second group of clock selection signals outputted from the edge appearance time adjustment circuit 103 to output a modulated clock signal MCK.

摘要翻译： 一种相位选择型频率调制器，能够缓和对调制时钟信号的相位范围的限制。 相位选择型频率调制器包括用于产生N相时钟信号的多相时钟信号发生电路101; 控制电路104，用于顺序地激活指示从N相时钟信号中选择的时钟信号的第一组时钟选择信号中的一个; 边缘出现时间调整电路103，用于调整从控制电路104输出的第一组时钟选择信号的上升沿出现时间和/或后沿出现时间，以输出第二组时钟选择信号; 以及调制时钟信号发生电路102，用于根据从边缘出现时间调整电路103输出的第二组时钟选择信号的激活状态从N相时钟信号中选择一个时钟信号，以输出调制时钟信号MCK 。

公开(公告)号：US06911850B2

公开(公告)日：2005-06-28

申请号：US10312882

申请日：2002-05-14

申请人： Junichi Okamura

发明人： Junichi Okamura

IPC分类号： H03L7/081 ,  H03L7/089 ,  H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H03L2207/14

摘要： In a semiconductor integrated circuit including a phase comparison circuit for a DLL in a reception circuit for receiving serial digital transmission signals, phase detection characteristics of the phase comparison circuit are improved while preventing false lock so as to improve response speed and locking accuracy of the DLL as a whole. The semiconductor integrated circuit includes series-connected delay elements each having a delay time which is controlled in accordance with a control voltage, a phase comparison circuit for generating a voltage corresponding to a phase difference between a clock signal input to a predetermined one of the delay elements and a clock signal output from another predetermined one of the delay elements, a control circuit for controlling the phase comparison circuit to generate a predetermined voltage when said phase difference is within a predetermined range, and a filter circuit for filtering the voltage generated by the phase comparison circuit to generate the control voltage to be applied to the delay elements.

摘要翻译： 在包括用于接收串行数字传输信号的接收电路中的用于DLL的相位比较电路的半导体集成电路中，改善了相位比较电路的相位检测特性，同时防止错误锁定，从而提高DLL的响应速度和锁定精度 作为一个整体。 半导体集成电路包括串联连接的延迟元件，每个延迟元件具有根据控制电压控制的延迟时间;相位比较电路，用于产生对应于输入到预定延迟时间的时钟信号之间的相位差的电压 元件和从另一个预定延迟元件输出的时钟信号;控制电路，用于当所述相位差在预定范围内时控制相位比较电路产生预定电压;以及滤波电路，用于对由 相位比较电路，以产生要施加到延迟元件的控制电压。

公开(公告)号：US06381186B1

公开(公告)日：2002-04-30

申请号：US09939586

申请日：2001-08-28

申请人： Junichi Okamura ,  Tohru Furuyama

发明人： Junichi Okamura ,  Tohru Furuyama

IPC分类号： G11C700

CPC分类号： G11C11/4085 ,  G11C8/12 ,  G11C11/401 ,  G11C11/4087 ,  G11C29/50

摘要： A dynamic random access memory includes a plurality of dynamic memory cells arranged in rows and columns, a word line connected to the memory cells on the same row, a bit line connected to the memory cells on the same column, a word line selecting circuit having a word line selecting function of selecting an arbitrary one of the rows in response to an internal address signal, a word line driving voltage source, a word line driving circuit having at least one driving MOS transistor connected between the word line driving voltage source and the word line, for driving the word line in response to an output signal of the word line selecting circuit, and a control circuit for, in response to a voltage stress test control signal input from outside, controlling the word line driving circuit so that the word line driving circuit drives word lines more than those selected in a normal operation mode upon receiving an external address signal.

摘要翻译： 动态随机存取存储器包括以行和列排列的多个动态存储单元，连接到同一行上的存储单元的字线，连接到同一列上的存储单元的位线，字线选择电路， 响应于内部地址信号，字线驱动电压源，字线驱动电路选择任意一行的字线选择功能，具有连接在字线驱动电压源和 字线，用于响应于字线选择电路的输出信号驱动字线;以及控制电路，用于响应于从外部输入的电压应力测试控制信号，控制字线驱动电路，使得字 线路驱动电路在接收到外部地址信号时，比在正常操作模式中选择的字线更多地驱动字线。

公开(公告)号：US06307796B1

公开(公告)日：2001-10-23

申请号：US09688083

申请日：2000-10-16

申请人： Junichi Okamura ,  Tohru Furuyama

发明人： Junichi Okamura ,  Tohru Furuyama

IPC分类号： G11C700

CPC分类号： G11C11/4085 ,  G11C8/12 ,  G11C11/401 ,  G11C11/4087 ,  G11C29/50

摘要： A dynamic random access memory includes a plurality of dynamic memory cells arranged in rows and columns, a word line connected to the memory cells on the same row, a bit line connected to the memory cells on the same column, a word line selecting circuit having a word line selecting function of selecting an arbitrary one of the rows in response to an internal address signal, a word line driving voltage source, a word line driving circuit having at least one driving MOS transistor connected between the word line driving voltage source and the word line, for driving the word line in response to an output signal of the word line selecting circuit, and a control circuit for, in response to a voltage stress test control signal input from outside, controlling the word line driving circuit so that the word line driving circuit drives word lines more than those selected in a normal operation mode upon receiving an external address signal.

摘要翻译： 动态随机存取存储器包括以行和列排列的多个动态存储单元，连接到同一行上的存储单元的字线，连接到同一列上的存储单元的位线，字线选择电路， 响应于内部地址信号，字线驱动电压源，字线驱动电路选择任意一行的字线选择功能，具有连接在字线驱动电压源和 字线，用于响应于字线选择电路的输出信号驱动字线;以及控制电路，用于响应于从外部输入的电压应力测试控制信号，控制字线驱动电路，使得字 线路驱动电路在接收到外部地址信号时，比在正常操作模式中选择的字线更多地驱动字线。

公开(公告)号：US06166975A

公开(公告)日：2000-12-26

申请号：US468314

申请日：1999-12-21

申请人： Junichi Okamura ,  Tohru Furuyama

发明人： Junichi Okamura ,  Tohru Furuyama

IPC分类号： G01R31/28 ,  G01R31/30 ,  G11C8/12 ,  G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C29/00 ,  G11C29/06 ,  G11C29/34 ,  G11C29/50 ,  H01L21/66 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4085 ,  G11C8/12 ,  G11C11/401 ,  G11C11/4087 ,  G11C29/50

摘要： A dynamic random access memory includes a dynamic memory cell having a transfer N-channel MOS transistor and a capacitive element for storing data which is connected to the transfer N-channel MOS transistor, a word line connected to a gate of the transfer N-channel transistor, of the dynamic memory cell, and a word line driving voltage source, to which power voltage is input for raising the input power voltage to generate a word line driving voltage. Also, the dynamic random access memory includes an address circuit for generating internal address signals in accordance with externally input address signals, a word line selecting circuit for decoding the internal address signals and outputting a word line selecting signal which varies within a range between the word line driving voltage and a ground potential, and a word line driving circuit for driving a corresponding word line in accordance with the word line selecting signal, the word line driving circuit being provided in correspondence with the word line and having a P-channel MOS transistor which has a source connected to a first node having the word line driving voltage, a drain connected to the word line and a gate to which the word line selecting signal is applied.

公开(公告)号：US5684321A

公开(公告)日：1997-11-04

申请号：US481828

申请日：1995-06-07

申请人： Junichi Okamura

发明人： Junichi Okamura

IPC分类号： H01L29/78 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L23/62 ,  H01L29/76

CPC分类号： H01L27/0248 ,  H01L27/0251

摘要： An input protection circuit is formed on a semiconductor substrate. A resistive element of an impurity diffusion region is electrically isolated from a main region of the substrate by a first double well structure. A bipolar transistor is connected to the resistive element which is electrically isolated from the main region of the substrate by a second double well structure. An input pad is connected to the bipolar transistor.

摘要翻译： 在半导体衬底上形成输入保护电路。 通过第一双阱结构，杂质扩散区的电阻元件与衬底的主要区域电隔离。 双极晶体管连接到电阻元件，电阻元件通过第二双阱结构与衬底的主要区域电隔离。 输入焊盘连接到双极晶体管。

公开(公告)号：US07158441B2

公开(公告)日：2007-01-02

申请号：US11008957

申请日：2004-12-13

申请人： Junichi Okamura

发明人： Junichi Okamura

IPC分类号： G11C8/00 ,  G11C7/00

CPC分类号： H03K3/0231 ,  G06F1/10 ,  H03K3/03 ,  H03K3/0322

摘要： A semiconductor integrated circuit in which multiphase clock signals having the same phase difference are supplied from a multi-stage differential ring oscillator to other circuits, the multiphase clock signals can be prevented from being degraded in waveform due to electrostatic coupling between wirings of the multiphase clock signals and also wired in as small an area as possible. The semiconductor integrated circuit includes: multiple stages of amplifier circuits, connected in a ring form, for performing oscillating operation; a logic circuit for performing logic operation on the basis of predetermined ones of output signals of the multiple stages of amplifier circuits to output a plurality of clock signals having different phases from each other and duties not equal to 0.5; and a plurality of wirings for transmitting the plurality of clock signals output from the logic circuit.

摘要翻译： 一种半导体集成电路，其中具有相同相位差的多相时钟信号从多级差分环形振荡器提供给其他电路，可以防止多相时钟信号由于多相时钟的布线之间的静电耦合而在波形中劣化 信号，并尽可能小的面积。 半导体集成电路包括：以环形连接的多级放大器电路，用于执行振荡操作; 逻辑电路，用于根据多级放大器电路的预定输出信号执行逻辑运算，以输出具有不同相位的多个时钟信号和不等于0.5的功能; 以及用于发送从逻辑电路输出的多个时钟信号的多个布线。